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Amplitude noise in LC oscillators
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I've found a solution as a pulse-biased oscillator. https://www.geotech1.com/forums/show...598#post264598
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Yup.
I know of a paper that says the very same thing, but their solution is completely opposite.
The very problem of phase noise, as opposed to amplitude noise, is that ... it is the same noise. The source of both phase and amplitude noise is the active component flicker noise, which is being mixed to the carrier frequency. The source of flicker noise is thus a consequence of an active component running in a linear regime. So either make it a switch, so it does not run in a linear regime which sources the flicker noise to be mixed, or make it super linear by a local feedback so that the flicker noise becomes weaker, as in application of a degeneration resistor which was a go-to solution for low phase noise oscillators until recently.
My solution works with a switch, and an independent zero crossing detector.
Knowing that both phase and amplitude noise stem from the same source is helpful for us, as there is a vast body of research in minimising the phase noise. What works for reduction of phase noise, also works with amplitude.
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I believe I've got the answer to this kind of flicker noise.
There are so called "pule bias oscillators" where the energy lost in the LC tank is restored by means of a short constant current pulse applied once per period.
I have found that the flicker in the usual oscillatpor is caused by differences in the phase of the energy feedback from one cycle to another. A precise and repeatable zero-crossing detector used to determine the moment of switching greatly reduces amplitude flicker.
I'll try to post an example simulation soon.
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None
Mine is avoiding 1/f sources completely - it is digital, yet resonant. Wonders of PLL at work.
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It may seem so, but if you look at my circuit you'll notice a current sink subtracting all the excess ampltude and passing only the top 3V of the peak to the amplifier. The flicker noise I was looking at is there. Set the vertical scale of your osciloscope to 2 or 3V per division, focus it on the peaks of the wave and tell me how much flicker you see there.Originally posted by Davor View PostA little bump...
My oscillator works, and amplitude is rock solid.
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A little bump...
My oscillator works, and amplitude is rock solid.Attached Files
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BTW, the ESR of "normal" capacitors is quite small, so no problem omitting it in simulation. ESR values of 10nF capacitors are typically under 1 ohm.
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You may try it, and I'd be glad to hear about your results.
However, if you don't apply some sort of delay compensation, your circuit will remain unstable. Regarding the noise generation, this anti-Colpitts topology seem to be the closest to the ideal as described in literature, because the current-intensive angle is very small, and hence the least prone to phase noise generation. Provided the delay is compensated, of course.
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Thank you Davor. I was ale to run the simulation. The current ad voltage at the tank are very much in accordance with my needs.
However, the ESR should be added to capacitors C3 and C4 to get a more realistic simulation.
By the way, the original circuit (first post) can also be adapted to work as "inverse Colpitts" as well.
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You'll have to be satisfied with a simulation for now. I had a few PLL oscillator builds that proved to work identical to the simulation, so I trust this one will work well just the same.
The thing I invented in a process is something I call "anti-Colpitts", where a capacitive divider is used instead of a series capacitor. A few things happen in a process.
- the tank oscillates with almost full natural Q-factor, and the losses are small;
- the amplitude is somewhat controllable without a series resistor;
- there is a current peak related with the switchover, and it resides at the top and bottom of a coil voltage, but its position can be adjusted;
- high Q tanks will produce sinus of high purity, and with little current consumption.
Because the switchover travels right of the sinus maximum in your oscillator due to the lag in driver transistors, I identified it as the main cause of phase and amplitude noise. For optimum results the switchover should be placed precisely on sinus maximum. I can achieve it by lag compensation using a PLL as a tank driver.
The PLL locks to the phase defined by coil voltage zero crossing. Because this phase is 90° off, the PLL's VCO generates 4x the frequency, and 90° phase for a driver is generated by 2 flip-flops. Adjusting delay of a VCO feedback compensates the delay generated by driver circuitry, and switchover happens at precisely sinus maximum.
Driver losses effects, and the crossover, are diminished by the tank capacitive divider, and because the tank Q-factor is marginally affected by this oscillator, the signal purity is surprisingly good.
Ask whatever you need.
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So you actually build the circuit rather than a simulation?Originally posted by Davor View PostI take back what I said about PLL not helping.
When oscillator is built with a PLL driving transistors in switching regime, the 1/f noise mostly disappears because transistors are not in a noisy linear regime. I made a circuit that seem to be quite stable, which runs a Musketeer coil (spice model) at over 80V. It draws 400mA as well.
I'll post the schematic tomorrow.
I'm looking forward to seeing it!
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I take back what I said about PLL not helping.
When oscillator is built with a PLL driving transistors in switching regime, the 1/f noise mostly disappears because transistors are not in a noisy linear regime. I made a circuit that seem to be quite stable, which runs a Musketeer coil (spice model) at over 80V. It draws 400mA as well.
I'll post the schematic tomorrow.
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Random noise is the simplest way to shift the signal along the resolution threshold. It comes with a noise penalty though.Originally posted by Qiaozhi View PostIt's always seems a little ironic to me how oversampling and decimation requires the signal to be noisy in order to increase resolution.
A better but more complicated approach would be to add a triangle wave to the signal, having a 1 bit amplitude and a period equal to the oversampling period. But this would defeat the purpose of oversampling which is to have a simple ADC converter. See https://electronics.stackexchange.co...google_rich_qa
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