Detection distance for a US nickel and quarter

[green]

Point 'a' should look like a Gaussian curve, as in the upper-left plot. 'out' is the first derivative of 'a', and again the upper-left plot show a classic response curve.

Question: did you intend U2 to invert the preamp signal? R8 is grounded.

U2 was the invert signal in another analysis (EF sample). Grounded it so I was just looking at a target signal.

[Carl-NC]

Point 'a' should look like a Gaussian curve, as in the upper-left plot. 'out' is the first derivative of 'a', and again the upper-left plot show a classic response curve.

Question: did you intend U2 to invert the preamp signal? R8 is grounded.

[green]

Starting to draw schematic for testing the large coils I'm making to see if I can detect a quarter at 24inches. Compared integrator I used for my last bench circuit and Eric's reply #55. What should integrator out waveform look like when target is swept across the coil? I look at point (a) with a voltmeter when plotting static targets and point (out) for sweeping targets.

Should have cut gain= 10 from the simulations.

Probably for bench testing it doesn't matter. What should it look like for a detector?

[liudengyuan]

Don't play these analog circuits anymore, it can't make an excellent machine. A single-chip microcomputer plus high-speed ADC is simple and effective, which can save a lot of cumbersome circuits

[green]

Back to the main subject of the thread. After further tests and comparisons with 'normal' and 'long' sample pulses, I have returned to the normal ones as being best. i.e. in the range 20 - 50uS. Samples of 100uS and upwards appears to give more signal on higher conductivity coins, but the benefit was outweighed by increased noise. Even with increased integrator TC, this was so. The best benefit appeared to be had by lengthening the TX pulse to 350uS.

Eric.

Interesting. Are you still using integrator https://www.geotech1.com/forums/atta...1&d=1590237972 reply #55. How much did you increase the integrator TC? Are you looking at integrator out with a scope to compare changes or something different?

[Ferric Toes]

Back to the main subject of the thread. After further tests and comparisons with 'normal' and 'long' sample pulses, I have returned to the normal ones as being best. i.e. in the range 20 - 50uS. Samples of 100uS and upwards appears to give more signal on higher conductivity coins, but the benefit was outweighed by increased noise. Even with increased integrator TC, this was so. The best benefit appeared to be had by lengthening the TX pulse to 350uS.

Eric.

[Ferric Toes]

What I actually meant was the higher the VGSoff is amongst my collection of J113 fets
is the higher the IDss of those fets

From my limited knowledge of semiconductor production techniques I would think that J111, J112 and J113 are all made as one batch and then sorted according to their electrical characteristics i.e.VGS(off), IDSS etc. The fact that they are all 'Process 51' supports this. Higher VGS(off) in a J113 results in a lower RGS(on) and hence a higher drain current; although this is a pulse measurement as per note 2 on the data sheet. This follows through to the J112 and J111. However, J110 is a different process and on a different page in the data book. Many of the characteristics are similar to the J113 but it does not work without modification to the source circuitry. It is 'Process 58' and encompasses J108, J109 and J110.

Yes, I have just noticed that toward the front of the data book, the various processes are listed, together with the die construction. The dies for Processes 51 and 58 are quite different

Eric.

[6666]

Yes, that is correct. J111 and J112 have higher turn off voltages and higher IDSS. On resistance is lower too. See data sheet. Scan_20200608.jpg

What I actually meant was the higher the VGSoff is amongst my collection of J113 fets
is the higher the IDss of those fets

[6666]

Yes, that is correct. J111 and J112 have higher turn off voltages and higher IDSS. On resistance is lower too. See data sheet. [ATTACH]50493[/ATTACH]

Eric.

Thanks Eric

[Ferric Toes]

After a bit more testing it looks like the jfets with the higher turn off voltage , have a higher IDSS, might try them first

Yes, that is correct. J111 and J112 have higher turn off voltages and higher IDSS. On resistance is lower too. See data sheet.

Eric.

[6666]

After a bit more testing it looks like the jfets with the higher turn off voltage , have a higher IDSS, might try them first

[surfdetector]

Thanks for that circuit Eric

Well this has been an interesting exercise.

I have tested 55 J113 jfets, not are all equal.
I tested them all for VGS(off),

Out of the 55, there were enough to group into some pairs and quads with matching VGS(off).
The VGS(off) varies between the pairs and quads groups, the lowest VGS(off) is 1.1 volts, the highest 2.7 volts

For the record the groups VGS(off) are 1.1-1.2-1.5-2.6-2.7 volts

Question now is - is it better to use the lowest or highest VGS(off), or doesn't it matter as long as they match ?

At least your results are well within the specs shown on the datasheet of -.5 min to -3 max.

[6666]

Thanks for that circuit Eric

Well this has been an interesting exercise.

I have tested 55 J113 jfets, not are all equal.
I tested them all for VGS(off),

Out of the 55, there were enough to group into some pairs and quads with matching VGS(off).
The VGS(off) varies between the pairs and quads groups, the lowest VGS(off) is 1.1 volts, the highest 2.7 volts

For the record the groups VGS(off) are 1.1-1.2-1.5-2.6-2.7 volts

Question now is - is it better to use the lowest or highest VGS(off), or doesn't it matter as long as they match ?

[Ferric Toes]

For the record, here is the schematic for the FET tester that I have used since the 1970's. vis the 741. Now, I would just use the 200ohm range on the multimeter with a fixture to plug in the jfet and which shorts the S to G. J112's also work fine and give a lower rDS(on). VGS(off) is a bit higher though, with a max value of -5V, but most read about -3V.



Eric.

[6666]

There is no issue with the rise time of the gate drive pulse. So Vgs pinch off and on resistance are the parameters for matching. I saw on Cscope schematic that FETs should be matched to within +/- 0.25V pinch off. FETs with close Vgs off having similar on resistance, well you could measure that by monitoring the Idss.

Thanks will check as well