Single capacitor integrator switch placement

[green]

Isn't the % modulation based on the sum of the two sample widths divided by the period?

I think you are correct for Eric's 1C. For a normal 1C it's just one sample width.

[dbanner]

Isn't the % modulation based on the sum of the two sample widths divided by the period?

[green]

Turned the lower switch off in my simulation. Gain=10, TC=Rfdbk*Cfdbk/%time on. Maybe the formulas for both switches on are correct?

[Ferric Toes]

This works better than any other integrator I have tried, and simple too for analysis. from reply #56

Analysis isn't simple for me, reason I tried a spice simulation. Another try with your integrator, sample time=50us and 100us. Still get .5V out for .1V in(gain=5). Integrator TC for 50us sample =.1034s. Integrator TC for 100us sample =.0517s. What do you mean by modulated? What is the formula for TC including sample rate and sample time? Reason for trying to understand your integrator. I have to make a Tx circuit with integrator to test the large coils I'm making to try to detect a quarter at 24 inches. Think I understand the formulas for a normal 1C integrator. Just wondering what the formulas are for gain and TC with yours if I try your integrator.

Including the simulation. Maybe someone can try to see what I'm missing.

Don't worry; I have never mastered Spice so can't help much in ths area. I have a simulation package of sorts called Electronics Workbench which was useful in some design areas including filters, but the computer that has it installed has failed and I have mislaid the CD Rom. I'm sure someone versed in Spice will come and help. I can then learn too. All I can say for sure is that with the board I am working on, this 1C integrator works extremely well and seems to filter out noise much better than I have used before. The system runs very quiet in spite of the noise generated by my LED lights. In contrast a Vallon VMH3CS is spitting all over the place.

Eric.

[green]

You have gain calculation of 2 x R1. For each sample period only one resistor is active to give a gain of 10. Other resistor is out of circuit. According to literature on sample hold circuits of this type the basic TC is that of the feedback R and the C, which for my values is 10.3mS. The overall TC is, however modulated by the on/off time ratio of the sample pulses.

Eric.

This works better than any other integrator I have tried, and simple too for analysis. from reply #56

Analysis isn't simple for me, reason I tried a spice simulation. Another try with your integrator, sample time=50us and 100us. Still get .5V out for .1V in(gain=5). Integrator TC for 50us sample =.1034s. Integrator TC for 100us sample =.0517s. What do you mean by modulated? What is the formula for TC including sample rate and sample time? Reason for trying to understand your integrator. I have to make a Tx circuit with integrator to test the large coils I'm making to try to detect a quarter at 24 inches. Think I understand the formulas for a normal 1C integrator. Just wondering what the formulas are for gain and TC with yours if I try your integrator.

Including the simulation. Maybe someone can try to see what I'm missing.

[Altra]

Yes, I've used the DG412 in a high-voltage transmitter running it at 40V or so. 3V logic still works fine.

Thank you.

[Carl-NC]

Thanks for pointing out this feature. I have a bunch of DG412s do you think the same would apply this part? The data sheet shows Vee and dgnd separate in the diagrams

Yes, I've used the DG412 in a high-voltage transmitter running it at 40V or so. 3V logic still works fine.

[Altra]

A bonus with these is even when the analog is 10V or +/-5V, you can still clock it with 3V logic which eliminates level shifters. Perfect for micro control.

Thanks for pointing out this feature. I have a bunch of DG412s do you think the same would apply this part? The data sheet shows Vee and dgnd separate in the diagrams

[Ferric Toes]

Thanks, I'll look at my simulation again. Must be doing something wrong, I got a gain of 5 not 10.

What is the formula for TC? Wondering if my simulation is wrong for TC also.

You have gain calculation of 2 x R1. For each sample period only one resistor is active to give a gain of 10. Other resistor is out of circuit. According to literature on sample hold circuits of this type the basic TC is that of the feedback R and the C, which for my values is 10.3mS. The overall TC is, however modulated by the on/off time ratio of the sample pulses.

Eric.

[Carl-NC]

There are better switches than the 'old' 4066 but not tried any as yet.

My preference is the DG441 which is 16 ohms but channel-to-channel is 0.5 ohm max. A bonus with these is even when the analog is 10V or +/-5V, you can still clock it with 3V logic which eliminates level shifters. Perfect for micro control.

[green]

Hi Green, I'm not quite clear on your question, or maybe I was not clear. The gain when sampling with either R1 or R2 is switched in, is the same. i.e.10 for the values I used. R1 must always equal R2 whatever the value. Same for the feedback resistors.

Eric.

Thanks, I'll look at my simulation again. Must be doing something wrong, I got a gain of 5 not 10.

What is the formula for TC? Wondering if my simulation is wrong for TC also.

[Ferric Toes]

Played with spice some more. The formulas work for the simulation values, not sure correct for any values. Should have ( ) around 2*R1 for gain left simulation.

Hi Green, I'm not quite clear on your question, or maybe I was not clear. The gain when sampling with either R1 or R2 is switched in, is the same. i.e.10 for the values I used. R1 must always equal R2 whatever the value. Same for the feedback resistors.

Eric.

[Ferric Toes]

That's very similar to a bipolar design I did a while back. Based on your original zero-droop demod, I added the negative sampler and extra feedback R. I did not use a trimmer and used 4066-type switches instead of JFETs. I agree, it works very nicely.

Yes, I would normally use 4066 type switches, but I am upgrading an old design for a customer and which uses jfets. For some years now I have run the timing circuits from +5v and -5V rails and used a 4047 timer which also drives the +5V inverter, hence inverter is synchronised. The 4066's also hang between the + and - rails. Still need the trimmer to get best EF cancellation. As the 4066 is a quad device, I parallel up pairs to halve the resistance to 45 ohms, which helps. There are better switches than the 'old' 4066 but not tried any as yet. It will be worth doing as 'on' resistance of some are down to 0.5ohm. A balance trimmer will not then be necessary.

Eric.

[Carl-NC]

This works better than any other integrator I have tried

That's very similar to a bipolar design I did a while back. Based on your original zero-droop demod, I added the negative sampler and extra feedback R. I did not use a trimmer and used 4066-type switches instead of JFETs. I agree, it works very nicely.

[6666]

This works better than any other integrator I have tried, and simple too for analysis

Thanks Eric.