AMX TX

[Teleno]

The droop rate does not depend too much on the quality of the simulation of MOSFET, it mostly depends on the amount of energy ABSORPTION of the ground and targets and its variations..

What we know for sure from real experimentations is that such a tiny droop measured at XMIT current level induces a HUGE signal offset at the end of the receive stages after a total gain of several hundreds. This dramatically reduces the range of measurement of the ADC before saturation.
This is the reason why we insist on defining a COMPENSATION mechanism.

Such high gains are unnecessary and counterproductive when using an ADC of 16 bit and up. Unnecessary because the noise level of the signal is already higher than the resolution of the ADC. Counterproductive because amplification reduces the dynamic range, the bandwidth, adds noise, offset and delays.

In my experience even the lower spec 10 bit ADC of an Atmega328P proved excellent sensitivity (0.3g gold nugget at 5cm, spiral monocoil) with a preamp gain of 17 using the internal 1.1V reference voltage plus software oversampling/decimation (64 samples to add 3 bits) and low-pass filtering.

[Carl-NC]

What we know for sure from real experimentations is that such a tiny droop measured at XMIT current level induces a HUGE signal offset at the end of the receive stages after a total gain of several hundreds. This dramatically reduces the range of measurement of the ADC before saturation.
This is the reason why we insist on defining a COMPENSATION mechanism.

This is the exact same problem encountered in a square wave drive VLF detector. A square wave TX voltage produces a triangle wave TX field, and ground then induces a square wave voltage on the RX coil. In other words, big offsets. It's really the same problem you encounter in sinusoidal VLF designs where the X-channel ground signal limits the dynamic range. In those designs, you simply limit the X-channel gain. In the square wave design, I was once looking at methods to dynamically buck out the ground component. I should go dig up those notes again.

[Tinkerer]

Can someone tell me what a reasonable droop rate is for this TX method? Say, for a 1-amp peak current. I've run some sims (and I never ever trust the MOSFET models) and I see 10uA/us droop, which I don't believe is real. That is, for a 1-amp pulse 100us wide it droops ~1mA. But I have not actually built one of these so I don't know how it really behaves. I'm just trying to get a handle on how big of a deal an induced offset will be.

AMX_SIMULATION_25turn_TX_coil.zip

The TX current can decrease or increase depending on the TX voltage setting.
When the TX voltage setting is just right, the TX current is nearly flat.
The losses are resistive including RDS of the Mosfets, resistance of the coil and cable.

In the simulation we added a RX circuit.
You will notice that if you change the K L1 L2 0.3, and/or R19, R10,R3, The absorption of the RX coil changes and correspondingly, the slope of the TX current changes.

Now, if you approach the coil to a target, the target absorbs some energy from the TX coil field. This is especially noted with large targets and ground. Again, this changes the TX current slope.

Changes in TX current slope produce an offset in the RX as seen in the added RX preamp. In this RX preamp, no offset adjustments are made. AMX_SIMULATION_50turn_TX_coil.zip

[Willy Bayot]

Can someone tell me what a reasonable droop rate is for this TX method? Say, for a 1-amp peak current. I've run some sims (and I never ever trust the MOSFET models) and I see 10uA/us droop, which I don't believe is real. That is, for a 1-amp pulse 100us wide it droops ~1mA. But I have not actually built one of these so I don't know how it really behaves. I'm just trying to get a handle on how big of a deal an induced offset will be.

The droop rate does not depend too much on the quality of the simulation of MOSFET, it mostly depends on the amount of energy ABSORPTION of the ground and targets and its variations..

What we know for sure from real experimentations is that such a tiny droop measured at XMIT current level induces a HUGE signal offset at the end of the receive stages after a total gain of several hundreds. This dramatically reduces the range of measurement of the ADC before saturation.
This is the reason why we insist on defining a COMPENSATION mechanism.

More than keeping the XMIT coil current CONSTANT, the compensation system is necessary to keep low and constant the signal offset at the ADC level.

[Willy Bayot]

The transition time (flyback width) directly depends on the RESONANT frequency of the circuit made of the COIL, its internal capacitance and the small capacitor connected in parallel.
For equal XMIT power voltage, the flyback increases when increasing the resonant frequency.

Increasing the XMITpower voltage while keeping the same resonant circuit, increase the coil current (and consumption) but also increases the flyback voltage.

We usually set the resonant frequency between 200KHz to 300KHz (period 5 to 7 µsec). This is a half-sine width (flyback) of 2.5 to 3.5µsec.

We adjust the external capacitor value to get this frequency with the given coil and adjust the XMIT voltage to stay just below the diode breakdown rating of the main MOSFET's.

[KingJL]

I have no problem using SiC FETs @ 1200-1500V. Whatever it takes.

I don't either... that might get you to around 1A.

Also, if the flyback is too high for the current you want to run, can't you just increase the parallel capacitance on the coil? Seems like this controls the transition slew rates and if you slow them down the flybacks decrease.

I had about 1.5nF inadvertently added (early in the development) and it reduced the flyback voltage to ~620V which allowed me to get to ~0.75 A if I remember, it also extended the transition from 1 us to about 1.8 usec.

[Carl-NC]

I have no problem using SiC FETs @ 1200-1500V. Whatever it takes. Also, if the flyback is too high for the current you want to run, can't you just increase the parallel capacitance on the coil? Seems like this controls the transition slew rates and if you slow them down the flybacks decrease.

[KingJL]

Can someone tell me what a reasonable droop rate is for this TX method? Say, for a 1-amp peak current. I've run some sims (and I never ever trust the MOSFET models) and I see 10uA/us droop, which I don't believe is real. That is, for a 1-amp pulse 100us wide it droops ~1mA. But I have not actually built one of these so I don't know how it really behaves. I'm just trying to get a handle on how big of a deal an induced offset will be.

I've got to run some tests in next couple days to evaluate my new cable for my SuperD and I will make some observations for you. However any current, with my MOSFETs (800 V) and TX coil (315uH, 0.6 ohm), greater than ~550 mA causes the flyback to break the MOSFET diode reverse voltage rating, resulting in a huge droop. With flyback below the diode breakdown rating, I have minimal droop, but I will try to quantify that for you. Unless you use some super HV rated MOSFETs (or other technology) the CC current goal must be limited with Paul's design. For all other operational modes other than CC, this limitation does not exist.

[Carl-NC]

Can someone tell me what a reasonable droop rate is for this TX method? Say, for a 1-amp peak current. I've run some sims (and I never ever trust the MOSFET models) and I see 10uA/us droop, which I don't believe is real. That is, for a 1-amp pulse 100us wide it droops ~1mA. But I have not actually built one of these so I don't know how it really behaves. I'm just trying to get a handle on how big of a deal an induced offset will be.

[Willy Bayot]

Then you have solved your issue! If you want to discuss further, then we probably should start another thread.

The issue was not fully solved. I just wanted to exchange ideas about the whole compensation subject since you have already explored it before..
Let's drop it for a moment, it will naturally come back on the table later in this project if we choose to use the CC approach.

[KingJL]

... The only method which worked was to capture the variations of offset levels at the end of the receiver stages and apply the corrrections of XMIT current based on those measurements.

Then you have solved your issue! If you want to discuss further, then we probably should start another thread.

[Willy Bayot]

I am not sure what you are saying... The current sensing amp (singular) is exclusively and continuously sensing/amplifying the input which is across the 0.033 ohm current sense resistor. In other words ("AT THE END OF THE RECEIVE CHAIN") what receive chain? In this case (INA293B3-Q1) is extremely accurate... that is what it is designed to do. Depending on the current range you need to be able to measure, you might need the C2(50x) or even the C1(20x) version. The timing accuracy and granularity of the ADC is wholly dependent on your microprocessor capability and your code.

Slight variations of the ramp generate large variations of signal offset at the end of the receiver stages. The regulation of the XMIT current should be precise enough to prevent the variations of signal offset in spite of the quick variations of energy absorption from the ground and targets. Moreover, the signal offset levels should be kept low by the regulation in order to apply a maximum amplification gain without saturation.
We have used the method that you described using about the same circuits as yours but we were unable to make the necessary corrections of energy losses with enough precision.
The only method which worked was to capture the variations of offset levels at the end of the receiver stages and apply the corrrections of XMIT current based on those measurements.

[KingJL]

I still have some doubts that it is possible to get a good dynamic regulation in this way AT THE END OF THE RECEIVE CHAIN after all the amplification stages...

I am not sure what you are saying... The current sensing amp (singular) is exclusively and continuously sensing/amplifying the input which is across the 0.033 ohm current sense resistor. In other words ("AT THE END OF THE RECEIVE CHAIN") what receive chain? In this case (INA293B3-Q1) is extremely accurate... that is what it is designed to do. Depending on the current range you need to be able to measure, you might need the C2(50x) or even the C1(20x) version. The timing accuracy and granularity of the ADC is wholly dependent on your microprocessor capability and your code.

[Willy Bayot]

Actually you can measure the slope of the current if you need or want to... it is all in the way you configure the input to the sense amp (hardware selection) and how you configure the (cpu) ADC capture timing (software).

Did you calculate what precision in time and value you can get from the measurements of the current on the two extremities of the ramp using an internal ADC (probably 10- or 12-bit) and your 100x gain amp?
I still have some doubts that it is possible to get a good dynamic regulation in this way AT THE END OF THE RECEIVE CHAIN after all the amplification stages.
If you have made real and successful experiments, I would be quite re-assured.

[Willy Bayot]

Most standard micro-processors now provide pulse timing generation with hardware-controlled complementary output and programmable dead-time with a 10nsec precision.
It is true for the STM32 family (Output Compare feature) which I personally experienced.
It is also true for the PIC32MZ, PIC32MK and ESP32 families.
No need for any interrupt features nlor FPGA capabilities. The timing schedule of each digital pin can be controlled from DMA and thus, completely in parallel processing with the rest of the application logic.

As Carl noted, varying the parameters of the timings on-the-fly to support multi-period waveform is more advanced and not necessarily suppported by all processor families.

I suggest that we first concentrate on an architecture which supports only a single period waveform at a time.