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  • KingJL
    replied
    Originally posted by Tinkerer View Post

    The superD coil assembly sounds very interesting. What kind of RX frontend did you use?
    Tony, Currently experimenting with direct sampling using low noise differential input buffer with 26db gain and Audio DAC... a work in progress. First issue I had was a suitable coil cable... now that is solved
    Did you use any ground compensation?
    Only ground compensation is in cpu code... call it DSP if you want, but I call it preprocessing before DSP.
    Is there any way to simulate the SuperD coil?
    Probably, but that is beyond my capability... I find it difficult to simulate any IB coil setup with the simulator(s) that I have available.

    Adding to the AFE mentioned above: I am following Carl's approach to the AFE and subsequent processing closely. I like the "current mode" configuration and I have always been a proponent of the AD797 (A few years ago, I actually modified my HH2 implementation to use a two stage preamp with a AD797 @ 12x as the first stage... I piggy backed 2 boards to implement the 2 stage preamp and supply the extra supply current that AD797 needed).

    Leave a comment:


  • Tinkerer
    replied
    Originally posted by KingJL View Post
    @moodz,
    I have actually built your circuit (using different components of course). I have been experimenting using a SupedD coil with 300uH @0.6 ohm TX (Rx are 375uH each). Current is maintained at 500 mA; TX voltage at 1.31V (higher than your 1.23, but probably due to slightly higher RDSon for the supply FETs that I used). Have tested with TX pulse trains of 20 KHz 10 KHz and 5 KHz. I have used no dead time in the TX signal train (which CAN in itself lead to "tilt"). ​I have experienced NO shoot-through issues and no tilt issues. What I love about the alt2hbridge circuit is the elegant simplicity and versatility of the circuit that does not require extraordinary efforts to overcome shortcomings present in other h-bridge circuits. If you stay with the relatively low current implementation (0.5 mA), issues like shoot through do not seem to appear (higher current devices also have higher gate capacitance, which affects switch on/off timings). There is more "bang for the buck" with a higher frequency TX train than higher TX current! And to minimize any effects of a "tilt" keep the low side resistance to an absolute minimum... that is where the losses occur... if you need resistance for current sense, put in the high side where it does not involve the coil discharge current! I am an advocate of improvement where there is actual realized "improvement"... I am also an advocate of "if it ain't broke... don't fix it"!
    The superD coil assembly sounds very interesting. What kind of RX frontend did you use? Did you use any ground compensation?
    Is there any way to simulate the SuperD coil?

    Leave a comment:


  • KingJL
    replied
    Originally posted by moodz View Post
    ... so I checked the "original" proof of concept circuit from the museum of projects layin around and it works as advertised.

    1.3 volts supply / 0.5 amps peak ( ie 1 amp swing ) / 520 volts peak / 1 microsecond flyback time.

    The coil is a minelab 0.5ohm 300uH mono.

    There is no current drawn with the coil disconnected so I am going to say that there is no shoot thru in the supply fets.

    The mosfets are nothing special IRF840 for the coil fets and IRL1404 for the supply switches.


    The CPU outputs a single TX pulse train at 15 Khz to a TC4428 mosfet driver chip that produces the inverting gate drive .. shown in the pic below.

    Measuring the tilt ... couldn't get a reading of any tilt ... so I am going to say it dont matter.

    PS .. if anyone can point out why tilt does matter AND point to a detector design ( not theories ) that uses tilt control I might reconsider that opinion ...

    moodz
    ​
    @moodz,
    I have actually built your circuit (using different components of course). I have been experimenting using a SupedD coil with 300uH @0.6 ohm TX (Rx are 375uH each). Current is maintained at 500 mA; TX voltage at 1.31V (higher than your 1.23, but probably due to slightly higher RDSon for the supply FETs that I used). Have tested with TX pulse trains of 20 KHz 10 KHz and 5 KHz. I have used no dead time in the TX signal train (which CAN in itself lead to "tilt"). ​I have experienced NO shoot-through issues and no tilt issues. What I love about the alt2hbridge circuit is the elegant simplicity and versatility of the circuit that does not require extraordinary efforts to overcome shortcomings present in other h-bridge circuits. If you stay with the relatively low current implementation (0.5 mA), issues like shoot through do not seem to appear (higher current devices also have higher gate capacitance, which affects switch on/off timings). There is more "bang for the buck" with a higher frequency TX train than higher TX current! And to minimize any effects of a "tilt" keep the low side resistance to an absolute minimum... that is where the losses occur... if you need resistance for current sense, put in the high side where it does not involve the coil discharge current! I am an advocate of improvement where there is actual realized "improvement"... I am also an advocate of "if it ain't broke... don't fix it"!

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by moodz View Post

    Measuring the tilt ... couldn't get a reading of any tilt ... so I am going to say it dont matter.

    PS .. if anyone can point out why tilt does matter AND point to a detector design ( not theories ) that uses tilt control I might reconsider that opinion ...

    moodz

    ​

    For more explanations, See post of Tony here:
    For the initial TX module I propose to use the schematic and PCB here https://www.geotech1.com/forums/forum/projects/differential-front-end-pi/408045-bipolar-alternative-to-h-bridge-generating-sine-waveforms-half-single-full?p=408376#post408376 and here https://www.geotech1.com/forums/forum/projects/differential-front-end


    Leave a comment:


  • green
    replied
    I added a coupling command, Tx to Rx with my spice circuit. Big change, tilt doesn't work. Removed Rx damping resistor, tilt worked but oscillates. Wanted to learn something, see I have alot to learn.

    Leave a comment:


  • Willy Bayot
    replied
    PS .. if anyone can point out why tilt does matter AND point to a detector design ( not theories ) that uses tilt control I might reconsider that opinion ...
    r

    Did you try to change the energy absorption of the coil by passing a large target over it?
    This is not a theory,.
    A tiny variation of tilt generated by this type of change generates in turn a large signal offset change after all the receiver stages.
    The variations of XMIT current tilt are not really disturbing but the large variations of signal offset at the receiver end are really disturbing the DSP.
    Everything was OK while testing on the bench.
    It is a surprise we got a few months ago on our real square wave project as soon as we went over a real ground.
    It is not even when there is a large target going under the coil, it is also happening while the coil is swinging with its slight variations of height over the ground.
    This behaviour is specific to the square wave system and does not appear on traditional triangular wave systems.

    Now, if you still want to ignore this fact, go ahead, you will have the same surprise as us!!!

    Leave a comment:


  • ivconic
    replied
    I'm curious about Carl's comment on that...
    ...
    "...
    TC4428 mosfet driver chip that produces the inverting gate drive..."
    Is it relevant at all? Inverting or not?
    I just checked with the local suppliers, the IR2103 is currently the only driver that can be found, albeit at a ridiculous price.
    It has high and low sides. In this case, the low side would be used.
    But I wonder; why use of driver?
    Can't logic level fet be used without driver?
    IRLZ44NN comes to mind, I have those...
    I worked with them and made constant current regulators and powered them with a signal directly from the Atmega...
    ​

    Leave a comment:


  • moodz
    replied
    ... so I checked the "original" proof of concept circuit from the museum of projects layin around and it works as advertised.

    1.3 volts supply / 0.5 amps peak ( ie 1 amp swing ) / 520 volts peak / 1 microsecond flyback time.

    The coil is a minelab 0.5ohm 300uH mono.

    There is no current drawn with the coil disconnected so I am going to say that there is no shoot thru in the supply fets.

    The mosfets are nothing special IRF840 for the coil fets and IRL1404 for the supply switches.


    The CPU outputs a single TX pulse train at 15 Khz to a TC4428 mosfet driver chip that produces the inverting gate drive .. shown in the pic below.

    Measuring the tilt ... couldn't get a reading of any tilt ... so I am going to say it dont matter.

    PS .. if anyone can point out why tilt does matter AND point to a detector design ( not theories ) that uses tilt control I might reconsider that opinion ...

    moodz

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    ​

    Leave a comment:


  • ivconic
    replied
    Originally posted by Carl-NC View Post
    At least 3 samples per response cycle, in order to look at curvature. Way back, I proposed a 2-frequency system of 5kHz and 25kHz, and sampling every 10us. That gives 2 samples per short pulse and 10 samples per long pulse. The long pulse is used for ground & iron ID and large gold, the short pulse for small gold.

    Yes, you can do it with analog demods. The above scenario requires 12 demods but you could cut back to even 6 (2+4).

    The motor controllers I've seen are basic H-bridge with no means for flyback preservation, so they shunt the flyback through the body diodes back to the power supply. Therefore you can never get a high slew rate. Might work for VLF, in fact I've use the DRV8872 H-bridge in a VLF design.
    Damn! I am out of luck today! All the misses!
    But you must admit that it looks so tempty!


    Leave a comment:


  • Carl-NC
    replied
    At least 3 samples per response cycle, in order to look at curvature. Way back, I proposed a 2-frequency system of 5kHz and 25kHz, and sampling every 10us. That gives 2 samples per short pulse and 10 samples per long pulse. The long pulse is used for ground & iron ID and large gold, the short pulse for small gold.

    Yes, you can do it with analog demods. The above scenario requires 12 demods but you could cut back to even 6 (2+4).

    The motor controllers I've seen are basic H-bridge with no means for flyback preservation, so they shunt the flyback through the body diodes back to the power supply. Therefore you can never get a high slew rate. Might work for VLF, in fact I've use the DRV8872 H-bridge in a VLF design.

    Leave a comment:


  • ivconic
    replied
    Specifications
    Input Voltage: 6 V to 27 V
    Current: 43 A (max)
    Maximum PWM Frequency: 25 kHz
    Protection: short circuit, over-voltage, under-voltage, overtemperature
    Logic Voltage: 3.3 V to 5 V
    ​

    Leave a comment:


  • ivconic
    replied
    Click image for larger version

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    The BTS7960 schematic...

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  • ivconic
    replied
    And now totally lunatic question, so I wont mind if everybody laughs on me now...
    What if I try to use full bridge motor driver as TX and place a coil instead a motor?
    Reason for asking is simple; plenty of various such drivers on local adverts, prices are affordable and all the control&protect logic is already included.
    Those are sold as "luxurious" modules, containing almost everything. No additional sweat at all.
    Made for "dummies" literally!


    https://novi.kupujemprodajem.com/pre...rds=H%20bridge

    Leave a comment:


  • ivconic
    replied
    Originally posted by Willy Bayot View Post

    50 Kps does not mean that we capture 50000 samples per cycle (period).
    Note that we do not throw away any cycle, each one is necessary to participate into the results and increase the final SNR.

    We need to get enough elements of the decay of each half-cycle to be able to study the decay shape (and make the discrimination and the ground balance using DSP).
    This could require to cut each half-cycle into slices of one or two µsec
    So, given a half-cycle of 20µsec (cycle at 25000kps = 40µsec), we would then need to capture a maximum of 20 accumulated samples per half-cycle.
    The 20 samples of a positive half and the ones of the following negative half are subtracted (since they are inverted in a bipolar system, it amounts to add them together).
    The results are then accumulated in a 20-slot demodulation array to make a digital integration during a time depending on the required frequency of net feed-back results.
    Let's say we swing at 1 meter/sec on average, this corresponds to a trip of the coil of 1mm during 1 msec.
    If we need to generate a feed-back to the operator every centimeter, we can accumulate the captures during 10msec.
    Thus, we can accumulate (integrate) 10msec interval / 40µsec period = 250 consecutive periods (with the corresponding amplification gain and reduction of random noise).

    It means in this case that the CPU has to only trigger its DSP calculations on the array of 10 accumulated samples every 10msec, which is largely acceptable for any type of existing micro-processor.

    However, the initial captures of the raw samples by the ADC should fast enough to get this raw capture rate (1µsec per sample).
    If necessary, it could be done with the help of DMA.

    ​​The above calculations can be repeated for each type of pulse rate. WIth a pulse rate of 5Kps, we get 100 accumumated samples per half-cycle and an integration factor of 10msec interval / 200µsec period = 50 consecutive periods​
    ​
    A little bit "condensed" explanation for my slow brain... yet after I break it down to several readings; hopefully I wll understand it and get used on such facts. Usually that's the case when I learn something new to me.
    Carl's words: "...25kHz is the plan, and you get 2 PI responses per cycle so effectively it's 50kHz..." confused me, "PI responses" especially, so skimly I understood it as "samples".
    Actually there will be more samples than 50k. At each of 50k you take several samples per decay. How many; Carl would say "as much as possible" I bet.
    Anyway, now is clearer. Thanks a lot for explanation, Willy!
    Now... you said something that I like: "...The 20 samples of a positive half and the ones of the following negative half are subtracted (since they are inverted in a bipolar system, it amounts to add them together)..."
    This means we will narrow down the total ammount of data, later to be processed.
    Can it be done with analog circuit instead of in code of mcu?
    (Carl will roll eyes on this, but I know why am I asking this)

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by ivconic View Post

    If I understand well; you are talking about 50 000 samples per cycle, right?
    25 000 from "positive" side and 25 000 from "negative" side.
    Impressive quantity of raw data!
    I now understand why it was insisted on those specs.
    Also I see that it will need the rest of processing with serious resources...
    Is it wrong to assume that decent percent of those 50k raw samples will be redundant?
    Powerfull mcu will process such quantitiy with no effort at all, I don't doubt that.

    I was wondering how to initially reduce that amount of data, discard unnecessary ones, and send the rest to an mcu whose performance is good enough to process it.
    ​Don't be surprised by my constant insistence on the "poor man's solution", I always like to see a wider variety of options.​
    50 Kps does not mean that we capture 50000 samples per cycle (period).
    Note that we do not throw away any cycle, each one is necessary to participate into the results and increase the final SNR.

    We need to get enough elements of the decay of each half-cycle to be able to study the decay shape (and make the discrimination and the ground balance using DSP).
    This could require to cut each half-cycle into slices of one or two µsec
    So, given a half-cycle of 20µsec (cycle at 25000kps = 40µsec), we would then need to capture a maximum of 20 accumulated samples per half-cycle.
    The 20 samples of a positive half and the ones of the following negative half are subtracted (since they are inverted in a bipolar system, it amounts to add them together).
    The results are then accumulated in a 20-slot demodulation array to make a digital integration during a time depending on the required frequency of net feed-back results.
    Let's say we swing at 1 meter/sec on average, this corresponds to a trip of the coil of 1mm during 1 msec.
    If we need to generate a feed-back to the operator every centimeter, we can accumulate the captures during 10msec.
    Thus, we can accumulate (integrate) 10msec interval / 40µsec period = 250 consecutive periods (with the corresponding amplification gain and reduction of random noise).

    It means in this case that the CPU has to only trigger its DSP calculations on the array of 10 accumulated samples every 10msec, which is largely acceptable for any type of existing micro-processor.

    However, the initial captures of the raw samples by the ADC should fast enough to get this raw capture rate (1µsec per sample).
    If necessary, it could be done with the help of DMA.

    ​​The above calculations can be repeated for each type of pulse rate. WIth a pulse rate of 5Kps, we get 100 accumumated samples per half-cycle and an integration factor of 10msec interval / 200µsec period = 50 consecutive periods​
    ​

    Leave a comment:

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