Let's made a PC-base metal detector with usb interface !!!

[Aziz]

Hi friends,

I have measured the noise density relation on some functional parts of the design. It will be very very difficult to achieve even at least 20 bit ADC resolution.

The best low noise part is the modulator. It generates only three times more noise than the sound card itself (grounded input pins). How does it come? The decoding focuses only to the modulation frequency with very short band width (few Hz). It comes close to the noise density of the modulator stage. The total decoded signal will therefore have less noise, which results in generating only three times more noise than the sound card.

The modulator can even be improved further regarding to the noise figure. The lowpass filter must go (all sound cards have their own lowpass filter). The switching noises are in excess of 100kHz - 4 MHz, which won't be seen by the sound card. All op-amps should be replaced with a dual op-amp NE5532 (instead of TL072). The inverting buffer resistors must be lowered radically (1 kOhm). The modulator op-amp can be stacked (dual op-amp) and the resistors must be lowered. This would result in noise density of appr. 30 nV/sqrt(Hz) at 3 kHz. Most noise will be produced from the inverting buffers of the modulator.

The drawback of inverting amplifier is obvious: the input and feedback resistors will produce more noise than the op-amp itself, if the input impedance is high. So the input impedance must be lowered as much as possible.

The most noise will come from the low frequency range (DC to 10 Hz). The affected fuctional blocks for this are: buffer/pre-amp, PGA, integrator and S&H stage. A highpass filter for these stages is a must have feature.

I will extend my software to measure the noise more precisely. I can locate then the critical noise sources. I also started with noise spice simulations to optimize the fuctional blocks further. So the designs needs to be revised extensively.

I will mod my modulator again (low noise type).


Aziz

[Aziz]

Hi all,

the development will be continued, as soon as I have an oscilloscope. It could last several weeks (ebay).
In the mean time, I am working on an improved S&H and other parts. Due to different polarity output of the integrator, the S&H have to work for both voltage rails now (sampling also positive voltages).

Aziz

[Aziz]

Hi all,

you might want to see the modulator output. The picture below shows the uncontrolled S&H output stages (drifted end positions, TX pulses not running) and the modulated output of the S&H channels.
The channel signals can be directly decoded in the laptop software. The phase of the modulation gives the polarity of the channel signal.

Aziz

[simonbaker]

Very impressive progress Aziz - appreciate the updates.

Cheers,

-SB

[Aziz]

Hi all,

after getting a good and positive result, it makes really sense to follow this project further. All the 3-4 month of work was worth to make the proof of concept and to get the answer to my initial question.

The presented modules have to be optimized further for right signal levels to get maximum dynamic range (increasing SNR). I will also try other circuit solutions to get better results.

The new microcontroller port assignments are as follows:

 
[B]Port A:[/B]
Bit  Description
0-7 not assigned yet
(planned to attach temperature sensor, potentiometers for GUI, battery voltage control, ...)
 
[B]Port B:[/B]
Bit  Description
0    not assigned yet (reserved for coil voltage controller)
1    TXout (transmit pulse gate output)
2    not assigned yet (reserved for coil voltage controller)
3    not assigned yet (reserved for coil voltage controller)
4    LED green (blinking signals operation)
5    LED orange
6    LED red (signals active TX)
7    not assigned yet
 
[B]Port C:[/B]
Bit  Description
0    S&H gate for channel 1
1    S&H gate for channel 2
2    S&H gate for channel 3
3    S&H gate for channel 4
4    Integrator: de-integrate gate
5    Integrator: integrate gate
6    Integrator: integration/hold capacitor gate
7    Integrator: feedback resistor/clear integrator gate
 
[B]Port D:[/B]
Bit  Description
0    USART (RxD)
1    USART (TxD)
2    INT0 input (cycle start interrupt trigger)
3    PGA MUX0 (select PGA input path)
4    PGA MUX1
5    PGA G0 (select PGA gain)
6    PGA G1
7    PGA G2
 
MUX1:MUX0
0    0    Signal from Pre-amp (gain: 30x)
0    1    Signal from buffered RX (coil signal, gain: 1x)
1    0    Signal from buffered TX (attenuated TX coil signal, 1:1000 or 1:2000)  
1    1    PGA off (zero output)
 
The TX signal attenuation is part of the coil dampening resistor divider.
 
G2:G1:G0 (binary bit combination of the PGA gain)
0  0  0: high gain (~ 35x)
..
1  1  1: low gain (~ 3x)
 
PGA gain depends on the hard wired feedback resistor network selection.

As you can see, the S&H and integrator share same port address. With the new PI-opcode instructions, these blocks can be accessed with very short latency and efficiency (reducing op-code size). The double access op-codes allow either break-before-make or vice versa operations.

With the new integrator, analog integration/deintegration/addition/subtraction of sample signals with any polarity can be made. It also allows 0, -1 or +1 multiplications to the PGA output.

A typical firmware op-code implementation size varies from 50 .. 100 bytes. The ATmega16 has 1 kByte SRAM, which should allow upto 512 bytes for complex implementations (even more as the stack won't use 512 bytes). This could be the first detector, which runs the firmware on the data RAM (flash rom and EEprom won't be programmed). A so called cpu in a cpu! The microcontroller won't have any analysis specific code (no patent infrigements here). The circuit modules also do not infringe patents, as they are all well known and classical circuit solutions.

The plug-in modules (PC/laptop software) will allow the user arbitrary mathematical expressions for signal processing. Only the end user is responsible for using not protected and patented ideas. This device is a ground anomaly detector and not seen as a P.I. metal detector. It is probably the first detector with the 24-bit ADC signal processing capability.


Now a lot of work begins right now.

Take care,
Aziz

[Aziz]

Did you ever see a XXL detector?

Here we go!

[Aziz]

Hello friends,

I made the general proof of concept: It is working!
No, this isn't a 1. april joke!

I have tested on the last PGA, integrator and S&H board (the new improvements are not implemented yet). Following single channel data acquisition test is made:
Cycle start
TX on (transmit pulse on)
Wait 96 µs
TX off (transmit pulse off)
Wait 8 µs (damping process)
Setup integrator as inverting amplifier (inverter), input disabled
Setup PGA (x3), MUX from pre-amp (20x at the moment), input enabled
Wait 1 µs (settling time of PGA and inverter)
Open inverter
Wait 1 µs (settling time of inverter)
Open S&H 1 (sampling enabled)
Wait 2 µs (settling time of S&H)
Close S&H 1 (hold channel 1)
Disable integrator (off)
Disable PGA (off)
End of cycle

The modulator gives a small triangle wave form on the sound card scope due to offset voltage errors. The amplitude is increasing on metal presence nearby the search coil. The integrator is changed into an inverter and only one sample is sampled for this test.

I will continue with the improved PGA, integrator/inverter and S&H board next time. I also need now an oscilloscope to observe the signals.

Aziz

[Aziz]

Hi Simonbaker,

Hi Aziz -

I'm interested in your patent concerns -- can you detail them? Are there particular patents you are in conflict with, which ones? How does calling it a different name change things? Which countries' laws are involved?

Keep up the good work,

Regards,

-SB

there aren't any patent concerns as long as we detect ground anomaly effects and expired, but patented metal detection search methods.
And there aren't any restrictions for private usage of patented methods.
Not yet.

Aziz

[simonbaker]

Hi again,

BTW, I also will add the option of direct coil voltage sampling. One more I/O line is necessary. This will give the option of reconstruction of the flyback voltage decay curve to see, whether the damping resistor is adjusted well or not. The PGA has now two input channels (from pre-amp and from coil). The PGA has a high voltage protection circuit on the second input channel, which allows voltages to measure up to 1000V.

The improved new design gives also the possibility of lower offset voltage errors and to set the output of PGA and integrator to zero (for auto calibaration purposes). It also gives the possibility to measure during transmit on pulses.

These major changes will totally need three I/O lines more.

Important notes:
Due to some patent related issues, this project isn't a metal detector anymore (sorry guys!). It is only purposed to detect and measure ground anomaly effects. It is becoming a geologist instrument. The hardware platform itself cannot be seen as a detector without the instrument implementation code (instrument op-code firmware, not meant as the firmware code of the microcontroller), which itself is invented and copyrighted by me. So watch out and keep attention, when somebody steals this idea. I regularly save my postings in case of stealing and patenting my ideas as an evidence! This idea should be seen as a public domain intellectual property now.



Aziz

Hi Aziz -

I'm interested in your patent concerns -- can you detail them? Are there particular patents you are in conflict with, which ones? How does calling it a different name change things? Which countries' laws are involved?

Keep up the good work,

Regards,

-SB

[Aziz]

Hi all,

I had to add one more input channel to the PGA. I also had to group the functional blocks to the I/O ports. This makes fast access possible (one I/O operation). So forget the I/O assignments above. It has totally changed.

I also had to implement a two bit multiplexer to the PGA to save one I/O line. The ground anomaly detector will detect ground signals during transmit pulse on and off times. Particularly during flyback voltage decays (most of ground response signals). I will sense flyback voltages up to 1200 V.

The capacitive load on the PGA input is getting to be a problem. These parasitic capacitances will pass small signals during switching transitions. As long as they be totally synchronized, it shouldn't be serious.

The integrator is a critical part. Particularly during switching, charge injection is a big problem due to parasitic capacitances of the JFET's (Cds, Cgs). I think, if carefully controlled, it shouldn't be serious as well (the holding capacitor can be controlled individually).

Now there is too much work to implement the new design before I can continue with the module tests. I think, it gives now the flexibility for every possible ground anomaly detection search modes.

I probably need to discriminate between ground anomaly and metal objects in the ground. Metal objects in the ground will definitely disturb the ground anomaly measurements. In this case, the user will be informed either to remove the metal objects in the search area before continuing with the ground anomaly measurement (no , do not do this!) or to measure elsewhere (most suggested option ).

Take care,
Aziz

[Aziz]

Hi all,

after excessive SPICE circuit simulations, the front-end receiver of the ground anomaly detector will consist of following stages:

Buffer (gain 1x)
Pre-amp (gain 30x)
PGA (3-bit gain control, gain 3-35x, 2-bit input mux control)

This makes the early sampling of ground possible, without getting the op-amp into saturation. Op-amp saturation has penalty delay time of 0.5..1µs or more (depends on many factor). The buffer can not come into saturation due to clamped input (over-voltage protection). This also applies to the PGA as this can be switched off. Only the pre-amp could be saturated in the early timings. The PGA has two input channels (buffer, pre-amp).

The pre-amp needs an offset voltage compensation adjustment.

Damn, that metal objects in the ground will disturb my ground anomaly detector heavily.

These design changes are too much at the moment and I am continuing now with the proof of concept.


Aziz

[Aziz]

Hi again,

BTW, I also will add the option of direct coil voltage sampling. One more I/O line is necessary. This will give the option of reconstruction of the flyback voltage decay curve to see, whether the damping resistor is adjusted well or not. The PGA has now two input channels (from pre-amp and from coil). The PGA has a high voltage protection circuit on the second input channel, which allows voltages to measure up to 1000V.

The improved new design gives also the possibility of lower offset voltage errors and to set the output of PGA and integrator to zero (for auto calibaration purposes). It also gives the possibility to measure during transmit on pulses.

These major changes will totally need three I/O lines more.

Important notes:
Due to some patent related issues, this project isn't a metal detector anymore (sorry guys!). It is only purposed to detect and measure ground anomaly effects. It is becoming a geologist instrument. The hardware platform itself cannot be seen as a detector without the instrument implementation code (instrument op-code firmware, not meant as the firmware code of the microcontroller), which itself is invented and copyrighted by me. So watch out and keep attention, when somebody steals this idea. I regularly save my postings in case of stealing and patenting my ideas as an evidence! This idea should be seen as a public domain intellectual property now.



Aziz

[Aziz]

Hi all,

it seems, that I have to build my PGA, integrator and S&H circuit board once again. The S&H will be changed into a non-inverting type. The gate drive of the JFET's will be slightly different in the S&H stages.

I even haven't tested the circuit board yet and it is becoming obsolete now.

The SPICE circuit simulations show good results.

Aziz

[Aziz]

Hi all,

regarding my last post, I will make the design changes now rather than later due to some tests I need. I will add a symmetrical buffer after the PGA output using a dual op-amp (NE5532).

The positive and negative buffered PGA output will then be fed into the two integrators gate JFET's (integrate, de-integrate).

The integrator will then be controlled from the PI implementation to be an either inverter, inverter with low-pass filter characteristics, integrator or de-integrator. The modifications will give unique flexibility to the PI implementation.

Aziz

[Aziz]

Hello friends,

when the proof of concept is done (positive result), I will then extend the hardware design slightly. I need the option of direct sampling of PGA output (integration disabled), inverted PGA output and extending the integrator into two channels (possibility for integration and de-integration of signals).

The JFET on the integrator capacitor (J2 I think) will be controllable to deactivate the integration feature (capacitor disconnected). When the discharge signal is set, the integrator acts as an inverting amplifier. The discharge resistor of the integrator will be set equal to the input resistor to make -1 amplification (inverting of PGA output). Then the PGA output can directly be sampled from the S&H stages. I need only two I/O control lines more for this feature and will make much more design flexibility possible.


Aziz