Let's made a PC-base metal detector with usb interface !!!

[Qiaozhi]

http://magsurvey.com/MetLSurveyHome.htm

Hi Unregistered,

Have you posted this link because you think it's relevant to the discussion of a PC-based metal detector with a USB interface, or is this just advertising?

http://magsurvey.com/MetLSurveyHome.htm

[Aziz]

I can even exceed the 24-bit resolution! With boxcar integrator technique!

Lets make some calculations:
fcycle: 750 Hz (750 pulses per second)
fsynch: 12 kHz
the lowest modulator frequency is: fsynch/2^4 = fsynch/16 = 750 Hz (ok, on every cycle a new sample will be taken).

The number of cycles per second is quite high. A fast-response detector. By lowering the detection response to 100 Hz, we can achieve a 7.5 times oversampling. The SNR will increase by a factor of sqrt(750/100) = sqrt(7.5) = 2.7 bits more resolution.

For pin-pointing, the response could even be lowered down to 10 Hz: 75 times oversampling = sqrt(75) = 8.6 bits more resolution.

This is what I am looking forward to achieve. There is even more potential by increasing the fsynch and fcycle slightly.

The CD4053 MUX has only three switches. I should probably make only three channel modulator. This also gives some more control lines from the micro and reduces the complexity a bit. I will think of this option.

Aziz

[Aziz]

Hi all,

a small bug in the frequency response of the triangular wave form is there:
It should be:
f(t) = (8A/PI²)*(cos(wt) + (1/3²)*cos(3wt) + (1/5²)*cos(5wt) + ..)

Sorry for this.

Now see the benefit of the triangular modulation shown in the picture below. Whereas the bipolar rectangular modulation contains in the first harmonics only 10.1 bits of 24 bit resolution of the information, the bipolar triangular modulation achieves with the same amount of harmonics 19.7 bits.
Taking four harmonics would achieve a resolution of 23 bits of 24 (triangular). The other modulation would achieve only 17 bits. The calculation is made upto 31 harmonics. Of course, the response is an infinite response. The table below gives just a good comparison.

Lower frequency modulations allow a better decoding (more resolution) due to more harmonics up to nyquist frequency (96 kHz/2 = 48 kHz). So the first (early) sample will be coded with lowest modulation frequency fsynch/16. The last sample will be coded with frequency fsynch/2 (containing anyway not much signal information besides lots of noise).

Effectively, there is a potential for 22-23 bits for decoding. Some bits for noise are reserved. So there is at least 18-20 bits of information for detection left. With some good sound-cards, we can achieve 22 bits perhaps.

Aziz

[Aziz]

Hi all,

here is some short basics of signal theory. Then you will understand, why I am going to use a triangle channel modulation. Please see the common topics and lectures presented in the internet anywhere (please google..).

I have four DC signals (samples), which have to be passed through one AC coupled line. No chance to pass DC signals directly. So therefore, all four signals will be amplitude modulated with an AC carrier frequency. The carrier frequency will be derived from the synch clock signal (driven from Laptop). Each channel has its own modulation frequency (fclk(n)=fsynch/2^n, n=1..4).

Best modulation wave form would be of course a pure sine-wave. It has only one frequency response:
f(t) = A*sin(wt + phi), A = amplitude, w = 2*PI*fcarrier, phi = phase

But to realize this in hardware is very very expensive. And the carrier frequency must be derived from the synch clock. So I would need four DDS chips (direct digital synthesis).


The easiest modulation wave form would be an alternating polarity rectangle wave form (changing from +A to -A). The frequency response is:
f(t) = (4A/PI) *(sin(wt) + (1/3)*sin(3wt) + (1/5)*sin(5wt) + ..)

As you can see, the whole channel information is spread over the multiple uneven harmonics in a linear way. The implementation of this modulation is quite easy with analog switches and performing a simple multiply of the analog signal with +1 / -1. The switching frequency would be the carrier modulation frequency.


Modifying the above modulation slightly by converting the modulator to an alternating integrator, it will generate triangular signal modulation. So the signal multiplied with the sign (+1/-1) will be integrated over each half carrier modulation frequency period. Triangular wave forms are almost looking like sine/cosine-waves. So it shouldn't have a much higher harmonic response. The frequency response is:
f(t) = (8A/PI)*(cos(wt) + (1/3²)*cos(3wt) + (1/5²)*cos(5wt) + ..)

As you can see, the higher harmonics contain less and less channel signal information and the first harmonics has the biggest information. The behaviour is quadratic. So the signal loss will be low, if we take a few harmonics to reconstruct the signal in the demodulator.

When each channel is modulated with its own carrier frequency, all four channels will be mixed together (adder). A filter after the mixer will reduce the switching noises but most sound-cards have its own anti-aliasing filter before digitizing. It is only intended to reduce the unused higher frequency noises (band limitting).

A frequency modulation is not convenient for this purpose (lock-in amp wouldn't work). A digital modulation isn't convenient as I have a pure analog signal interface (four DC signals). A time frame multiplexing (TDMA) would make the synchronisation complex and difficult. So I am using the simplest modulation technique.

That's the basics, why I am going to use the triangular amplitude modulation. The signal losses will be low by keeping the modulator as simple as possible.

Aziz

[Aziz]

Hi all,

the DC/DC charge pump is running. The practical results showing exactly same behaviour of the simulated results. It can deliver at least +50 mA and is more than I need. It will be clocked with the inverted synch clock (buffered through the inverter). I blew up a 100 µF capacitor (ouch! wrong polarity ).

The power budget at the moment:
- Voltage regulators: -5V, -9V, +5V
- DC/DC charge pump
- synchronisation module (without channel modulator)

Total: ~25 mA at 12 V battery supply.

Considering to change the -9V to a -5V. I do not need such a high voltage rail. The sound-card interface needs only up to 1 Vrms and the +5V/-5V supply rail is just enough. Two same voltage regulators are easier to handle and to get.

Now the next interesting topic: the channel modulator

Aziz

[Aziz]

Hello friends,

I have built the synchronisation clock generator and it is working quite well. Thanks to LTspice, which made the extensive prior testing and implementation possible. No significant clock jitter is happening. The lock-in amplifier is working with the synch module absolute stable and I can start with the channel modulator part soon.

The extracted synch clock is superiour (~50% duty cycle), which can directly drive the DC/DC charge pump without beeing divided by 2 (q1). I will probably lower the modulator frequency by a factor of 2 or 4 to achieve more resolution. The modulated channel information is distributed in the multiple harmonics of modulation frequency and I can therefore sample this from the ADC (with lock-in amplifier up to 12 kHz and with FFT up to 48 kHz).
This will help not loosing much bits of the ADC resolution due to modulation. The 24-bit PI is getting more realistic.

Now focusing to the DC/DC charge pump. I have now the clock signal for it.

Aziz

[Aziz]

Hi all,

I will go on with the below clock generation modules coming days. The schematics is already simulated and tested with LTSpice. Both channels can be operated individually. Right channel is for the modulator and DC/DC charge pump. So the right channel could run first to drive the DC/DC charge pump and to build up the +5V analog power supply. Left channel is for triggering the cycle start and synchronizes the clockings of the modulator stage on every cycle. The modulator is not shown yet. Minor changes could happen.

Aziz

[Aziz]

Hello friends,

I designed a combined dual LDO sharing the same reference voltage.
The LDO I made would need 4 op-amps, 1 reference voltage, 1 p-channel, 1 n-channel MOSFET and some resistors and caps.

However, the simple 78L05 sitting on the charge pump side had quite good results by keeping the total design simple (low ripple noise). So there wasn't any significant improvement and I will let the 78L05 for the simplicity and cheapness. I also tested the LT1086-5 and the 78L05 seems to have a better performance.

The power supply board is already built except the DC/DC charge pump (need clocking). I will focus now on the synch clock extraction from the sine wave output of the sound-card. Then I can test, whether the synch is stable (K.O. critical section).

Aziz

[Aziz]

Hi all,

I am focusing now on the analog power supply section. Particularly the 78xx and 79xx voltage regulators have too much dropout voltages. What a waste of energy.
So I have decided to develop my own linear low-dropout (LDO) voltage regulator (dropout < 200 mV) with +2.5/-2.5V reference voltage buffers for later purposes. My negative voltage will be very likely -10V and positive will be +7 or +8V (depending on the current draw). I want to use the extra voltages to have more dynamic range. Some op-amps aren't rail-to-rail types. So extra voltages are welcomed to have the full -5/+5 V rail. The -10V is necessary to switch the JFET's.

For the micro, the 7905 or 79L05 is quite enough. 12-5 = 7 volts will be converted to heat for cold days.

It is quite interesting to see and to know, how such a LDO circuit works. One can learn a lot.

Aziz

[Aziz]

Hi all,

I had to search for a better totem-pole driver and I have revised the discrete DC/DC converter (synchronized charge pump). Now the dead-time (battery short circuited state between switching transitions) is kept low and the efficiency is higher. It uses two same NPN transistors in the driver stage and has lower matching demands (not complementary BJT needed anymore).

It delivers now more current and higher voltages. Probably I could increase the +5V analog power supply few volts. It depends on the total current draw of the positive power supply. The new charge pump generates lower ripple noises.

It delivers from a 12 V battery supply a current of 42 mA at 8.5 V. See the schematics below for details.

Aziz

[Aziz]

Hi all,

I will start with the experimental PI hardware soon. I have decided to make splitted (modularized) boards. This gives the most flexible experimenting possibility. The boards will be plugged together and can be exchanged quickly for different configurations or alternate circuits. I will start with the power supply and the synch clock generation board. The clock synchronization is critical and the jitter has to be very low. I will see, how good this can be achieved.

Aziz

[Aziz]

Hello friends,

I did many simulations on PI damping process last days. Well, I had some suspect on my previous results and had a look deeper to the internals and indeed there was a mistake in my last simulation. I am sorry for this. The damping process for a 300 µH coil itself takes from the avalanche breakdown voltage of the MOSFET (400 V) down to the diodes clamping voltage of 0.65 V roughly 2µs.

But I have found some improvements on classic anti-parallel diode clamping. Particularly, the series resistor Rs to the clamping diodes should not be 1k or even lower. It should be higher not to modify the damping process with the damping resistor Rd. A value of 5-10 k will induce higher target signal responses. Particularly small time constant targets will benefit from the higher series resistor Rs. A change from 1k to 6k for instance will produce 3 times higher target response. The factor is dependend on the time constant of the target and is not linear to the value of the series resistor Rs.
During the clamping process, the series resistor Rs is connected parallel to the coil and damping resistor Rd. And this lowers the effective damping resistor, in which the damping process will be delayed (coil is becoming overdamping). The slope (first derivation) of the coil damping voltage will decrease and cause therefore lower target signal stimulation.
Increasing the series resistor Rs has an effect of increasing the thermal noise on the amplifier input stage. But the higher target signal induction has much more benefits and will compensate by far the higher noise on Rs.


Aziz

[barry]

Wow Az. That sounds like a great front end. Looking forward to see how it is done.

[Aziz]

Hello friends,

Next excursion into topic: analog front-end, pre-amp, front-end blocking/clamping

I tried to improve the signal quality of the analog front-end. And I have found a method, which doesn't need the front-end blocking via switching FET's nor the normal diode clamping. Usually, a 1k resistor followed by anti-parallel diodes will be used to clamp the overvoltage signal from the coil.

A new clamping circuit will be used, which prevents the saturation of the pre-amplifier and allows a sampling at 2 µs. The pre-amp need no any clamping diodes on the feed-back path.

This method will also work with "ringing" coils (underdamped PI coils), which doubles the signal quality by rectifying and filtering the ringing signal.


Aziz