GOLDSCAN 5 SCHEMATIC QUESTION

[dbanner]

O.K. Good to know this.

[Idefix]

Hi,
When Drain and Source can be swapped , it is indicated in the datasheet. like ther in a fairchild J113 datasheet.

https://www.fairchildsemi.com/datasheets/J1/J111.pdf

But, on a 2005 ONSemi J111, J112 datasheet , it is not indicated.

http://www.onsemi.com/pub/Collateral/J111-D.PDF

so, don't swap in this case.

Today, Fairchild is inside Onsemi.
So ?? in the doubt, don't swap.

[dbanner]

As I recall, I think there was an issue with that on GS4 schematic and they were swapped. They issue was the orientation of the jfets but can't recall which thread it was discussed. I'll have to do some digging.

[eclipse]

Looking into the GS4 schematic by Alex J113 drains are connected to GND.
This is not a big deal as these are bidirectional but do you think Drain and Source of the J113 are swapped?

[Idefix]

Hi,

The audio part is on the upper board, if I understand. Have you others pictures than these on this thread? it is hard to make a schematic with only few pictures.

As I saw, the audio uses an AD654 , wich is quite rare today in DIL, more easy in SO8. The price seems about to 8 €.

May be an easy way will be to use an LTC6990. Cheaper , about 2€ , and can make the same job.

http://cds.linear.com/docs/en/datasheet/6990fc.pdf

https://www.digikey.fr/products/fr/integrated-circuits-ics/clock-timing-programmable-timers-and-oscillators/689?k=LTC6990

[dbanner]

Yes, I see three 1K resistors, one in series with output, makes perfect sense. Had to use electrodroid app on my android phone to read those pesky 5 band resistors though. I think the schematic is very close to what it's supposed to be. Working through stage by stage is the right approach.

[Jose]

It looks like it's 47nf, instead of 100 nf. It was observed along with three 1K resistors, close to the gain control.
Apparently a 1K resistor is missing in the scheme, this would be in series with the TLC2262 output and the audio input on the other missing board.
Something similar to the GS4 scheme, (between GND pot and pin 3 of 1/4 IC3)
Jose

[eclipse]

Well perhaps the 47nF cap on the PCB is marked as 100nF cap in the schematic, and there are no other caps missing there.
Exact value probably is not that important (47nF-100nF).

[dbanner]

Yes, and there's a 100nF on shematic that isn't anywhere near the TLC2262 on board.

[eclipse]

It's just where the 47nF cap is located and it isn't used in the schematic.

[dbanner]

I also see TLC2262 on original instead of TL052 on schematic.

[dbanner]

Here are some pics of original GS5 issue 1 mainboard. The audio board is a seperate circuit board. I have some more pics somewhere but can't seem to find them right now. As for timing sequence, A goes to inverting(-) input, and the rest you can see from the GS4 schematic.

[eclipse]

You are right, C8 should not be used. Now for the C9 I guess it wont hurt to try to see any good - there's a capacitor on this photo 47nF which I don't think is accounted for in the circuit and it's in the vicinity of this op amp: http://www.geotech1.com/forums/attac...8&d=1498826015

[Jose]

For example don't you guys think there should be a cap (47-100nF) on these 2 spots:

I think the important thing is that we have a positive value signal in the output of both channels, when a metal is approaching the coil.
In the case of the GB or Iron channel as it is usually called, this signal must be measured before the reverse stage.
With respect to the capacitors in GS5, in IC2.2; IC2.3, I think it should not exist because it would create different integration times, since in the GB channel, the gain is adjustable.
Unlike GS4, the gain in both channels is fixed.
The other capacitor in IC1.1, would not know what to answer.
Jose

[eclipse]

For example don't you guys think there should be a cap (47-100nF) on these 2 spots: