Ground balance

[Carl-NC]

S2-all should be 200us after S1-all, the same as between S1-geb and S2-geb. It will work with a shorter delay but will reduce depth and Earth field cancellation may not be as good.
I don't know what A and B are for but it looks like the delay between them is set by R62 and C26. The delay between C & D are set by R60 & C24, so the A-B delay should be the same as the C-D delay. If these correspond to the S1-S2 pulses then that would be correct.

[pustareka]

Privet Bayu.Zdravo.Hello.

google say:

"The width of the Tx pulse is 200 microseconds. After 10 microseconds, you take first sample with a width of 15 microseconds, followed by a break of 45 microseconds. Then you take second sample with a width 15 microseconds.This is for all metal mode.
Ground sample you take 5 mictoseconds after end of first sample in all metal mode. This is first ground sample with a width 15 microseconds. Then there is a break of 200 microseconds after first ground sample.Than you take second ground sample with width 15 microseconds. Minimal delay between tx pulse and fitst sample in all metal mode is 7.05 microseconds. This is VR15=0 VR16=0 R61=4К7. Мaximum 37.05 microseconds. This is VR15=10К VR16=10К R61=4К7."

Uspehov. Uspeha. Succes.

[Bayu]

hello everyone, I'm working on 2 schemes, vlf and pi, all of them I'm still having problems with the ground balance, for PI I'm working on gs5, in this timing scheme there is something that makes me confused; how to change the timming width between A and B. what components do I need to change? because in the guide in the title gs5 I found the timming width was 45us while in my oscope it was 96us,

[Bayu]

wow there are so many reviews about GB I am also trying to simple GB using one IC, it just works less than perfect, I tried to plug it into polones, thanks master for the discussion

[green]

Thanks, first thing I did wrong was not look at U3 out to see it wasn't going fill scale. I use the same circuit(different switches)and didn't think I had a problem. Adding 23.8mV to +in U2(simulation) solves the offset. I have offset trim pots on my amplifiers and was correcting the offset. Need -1.2mV offset at invert amplifier out(normal out=zero) to zero integrator out with my circuit. Wasn't thinking about the trim pots when I asked the question reply #88.

Playing this morning. Trim pots to adjust amplifier out can adjust integrator out to zero. If timings are changed, integrator out changes. Important to have low charge injection.

[KingJL]

That is curious... 1612 NC contacts... 1611 NO contacts.

Sorry about that... just the opposite 1611 NC... 1612 NO.

[KingJL]

Tried the 1611 in the simulation, no difference.

That is curious... 1612 NC contacts... 1611 NO contacts.

[green]

First, are you sure you want to use the ADG1612 (vs. maybe the 1611)?

on edit: corrected ADG vs ADC.

Tried the 1611 in the simulation, no difference.

[green]

Hello green

Looking at your sims mate,now i am no where near as savvy as you when it comes to LTspice but as far as i can tell sim "A2=1_sw" appears to be ok,i get similar wave forms on my project in noisy environments,as for sim "A2=1_ADG1612" well it appears to be fine as well,its doing exactly what its supposed to be doing,except the circuit has a problem...Charge injection ! Charge injection is a characteristic of analog switches,each time the switch turns on or off it adds a small charge to the signal,and this charge always has one polarity,this results in a DC offset appearing on the output of the integrator,the more samples you have within a cycle the bigger the offset gets,some analog switches are nasty when it comes to charge injection,but there are some good ones as well,unfortunately the integrator in your sim has a DC offset on the output of about 540 mv,that's enough to drive the following stage to the rails,to continue with your sim just reduce the gain in the last stage.

Thanks, first thing I did wrong was not look at U3 out to see it wasn't going fill scale. I use the same circuit(different switches)and didn't think I had a problem. Adding 23.8mV to +in U2(simulation) solves the offset. I have offset trim pots on my amplifiers and was correcting the offset. Need -1.2mV offset at invert amplifier out(normal out=zero) to zero integrator out with my circuit. Wasn't thinking about the trim pots when I asked the question reply #88.

[KingJL]

First, are you sure you want to use the ADG1612 (vs. maybe the 1611)?

on edit: corrected ADG vs ADC.

[ZED]

Hello green

Looking at your sims mate,now i am no where near as savvy as you when it comes to LTspice but as far as i can tell sim "A2=1_sw" appears to be ok,i get similar wave forms on my project in noisy environments,as for sim "A2=1_ADG1612" well it appears to be fine as well,its doing exactly what its supposed to be doing,except the circuit has a problem...Charge injection ! Charge injection is a characteristic of analog switches,each time the switch turns on or off it adds a small charge to the signal,and this charge always has one polarity,this results in a DC offset appearing on the output of the integrator,the more samples you have within a cycle the bigger the offset gets,some analog switches are nasty when it comes to charge injection,but there are some good ones as well,unfortunately the integrator in your sim has a DC offset on the output of about 540 mv,that's enough to drive the following stage to the rails,to continue with your sim just reduce the gain in the last stage.

[green]

Tried a spice simulation using analog switches. What am I doing wrong?

[liekwang]

I found this schema is anyone already using it,

[green]

Separately, if one was to adopt the changing GB target sample width approach to ground balancing, wouldn't this enlarge the target "hole"?

Hi Elliot
Looked at Excel analysis again, looks like A2 gain=2 is a little narrower than A2 gain=1. I have been using A2 gain=1. Adjust first delay to desired delay time and adjust target sample to balance ground signal with second delay=4us and ground sample=100us. Did an Excel analysis, adjust first delay to desired delay time and adjust target sample to balance ground signal with second delay=20us and ground sample=50us. A2 gain=2, a little narrower, maybe a little more noise?

Wondering what sample times others adjust and leave fixed when ground balancing.

[green]

Hi Green, What are the advantages of having a 3 stage integrator circuit as you have ?

Good question, only reason I can think of. If I want more or less total gain, can change input resistor(100k) to second stage and not effect frequency response.