Balanced VLF Tx

[dougAEGPF]

errr ... actually PJ is right ... some multilayer topologies are particularly bad for radiating harmonics ... esp 4 layer.

[ATTACH=CONFIG]21783[/ATTACH]

A 4 layer board with NO power plane will be much better.
dougAEGPF

[dougAEGPF]

errr ... actually PJ is right ... some multilayer topologies are particularly bad for radiating harmonics ... esp 4 layer.

[ATTACH=CONFIG]21783[/ATTACH]

If ANY board is poorly designed then their can be a multitude of problems when its populated! But PJ made a blanket,unqualified statement and unlike you has never provided any explanation!He made it in connection with the QED inferring that the QED had harmonic problems because it used multilayer boards on 1 REV. This was and is completely untrue!

dougAEGPF

[Aziz]

Good morning guys,

*LOL* got a nightmare on parallel diodes (I think). Oh yes, there was something about evil parallel diodes...

If we would have a DC current path, then we would have connected them parallel through the coil. But the magic(tm)(hocus)(pocus) in the circuit is producing an AC voltage supply for the oscillator (half sine waves).

I hope, that the "parallel diodes" cause enough imperfections to the circuit, so that the oscillation can start. In normal operation state, these parts are becoming parasitic capacitances. But they are very important to protect the circuit (transistors) at the startup process.

Aziz

[moodz]

I agree with everything you say! But remember PJ is the same guy that has claimed that multi layer SMF boards are inherently bad because they generate harmonics!!!

dougAEGPF

errr ... actually PJ is right ... some multilayer topologies are particularly bad for radiating harmonics ... esp 4 layer.

[dougAEGPF]

It's not often I stick my nose in on stuff like this but FFS PJ your just another Troll on a mission to annoy people, me included having to read this rubbish.

Do you even understand the term parallel hmmmmm, the zeners in question have got some inductance/resistance via the c-tap coil.

I agree with everything you say! But remember PJ is the same guy that has claimed that multi layer SMF boards are inherently bad because they generate harmonics!!!

dougAEGPF

[mickstv]

So your saying them 2 diodes are not hooked up parallel?

And watch your mouth Aziz. You already have 2 strikes my friend!

It's not often I stick my nose in on stuff like this but FFS PJ your just another Troll on a mission to annoy people, me included having to read this rubbish.

Do you even understand the term parallel hmmmmm, the zeners in question have got some inductance/resistance via the c-tap coil.

[Aziz]

So your saying them 2 diodes are not hooked up parallel?

And watch your mouth Aziz. You already have 2 strikes my friend!

PJ, ask your mentor if you don't know the answer. But tell him, that this genius(tm), beautiful(tm) and simple(tm)(kiss) "invention" is already public domain.

Aziz

PS: I want to smoke the same stuff. Must be a strong stuff.

[PATCHES JUNIOR]

I don't know, what you are smoking PJ. Can I have the same $.hit?

I need two zener diodes, so each transistor is protected during the start-up process. In a normal operation, the zener diodes shouldn't break down. If so, take high voltage rated parts or reduce the supply voltage.
Aziz

So your saying them 2 diodes are not hooked up parallel?

And watch your mouth Aziz. You already have 2 strikes my friend!

[Aziz]

Good try Aziz, but they are in a circuit hooked up "parallel" to each other. So stop with the crap Aziz. Any one can see what I am talking about. You know better!

I don't know, what you are smoking PJ. Can I have the same $.hit?

I need two zener diodes, so each transistor is protected during the start-up process. In a normal operation, the zener diodes shouldn't break down. If so, take high voltage rated parts or reduce the supply voltage.
Aziz

[PATCHES JUNIOR]

PJ,

no, not connected parallel of course.
Each transistor has it's own voltage protection zener diode (same type).

That was the reason, why I have updated the schematics to avoid misinterpretation.

Aziz

Good try Aziz, but they are in a circuit hooked up "parallel" to each other. So stop with the crap Aziz. Any one can see what I am talking about. You know better!

[Aziz]

Don't tell me them there diodes ( D2 & D3 ) are in parallel with each other!!

PJ,

no, not connected parallel of course.
Each transistor has it's own voltage protection zener diode (same type).

That was the reason, why I have updated the schematics to avoid misinterpretation.

Aziz

[PATCHES JUNIOR]

See below, what I mean with the zener diodes. But select appropriate zener diodes (39 V for instance).

[ATTACH]21781[/ATTACH]

[ATTACH]21782[/ATTACH]

I personally like the PNP-variant as the coil voltages and center-tap is referenced to GND.

Cheers,
Aziz

Don't tell me them there diodes ( D2 & D3 ) are in parallel with each other!!

[Aziz]

See below, what I mean with the zener diodes. But select appropriate zener diodes (39 V for instance).





I personally like the PNP-variant as the coil voltages and center-tap is referenced to GND.

Cheers,
Aziz

[Aziz]

Ok, sorry my bad. The circuit gets better with better high voltage protection of the transistors.

Remove the zener diode in the circuits above and connect two zener diodes to emitter-collector connection of the transistor (each transistor needs its own zener diode). Select the zener voltage so, that the maximum voltage of the transistor doesn't exceed the specification limit.

Another issue: Start-up of oscillation. If the oscillator doesn't oscillate, we can bias the transistors with slightly different resistors. That requires two additional resistors however.

I have to build a test circuit to see the main issues.
Cheers,
Aziz

[WM6]

Really beautiful simplicity (ingenuity) Aziz - you will destroy "industry".