Target response tester

[Ferric Toes]

I have no Spice either, so I too am missing information with the .zip files.

I am building the logamp described in the applications data for the Burr Brown VCA610. It will be interesting to see how this approach fares.

Eric.

[green]

No Spice, I have occasionally been curious about simulation, but never enough to bother trying it.

It seems practical problems like real-world noise limit how much of a range you need, so maybe trying to perfect the low-level input behaviour of this discrete amp is not productive?

Thanks again for your help. Building the log amp in spice helped to understand what I needed to do. When testing the log circuit the other day I would sometimes get more than 800mv log out. 2.5 volts in(+PS) should be 800mv log out. After more time than it should I finally determined the scope over ranging was causing the problem so I added a resistor and diode to clamp the output going to far negative. Wasn't thinking when trying the capacitor decay, the clamp was causing the problem. Including schematic of log amp, if I had done sooner someone would have seen the problem. The 1usec decay looks like it could be better, need to try higher current. The diode is disconnected from common for todays tests. I tried a amplifier(offset adjusted to less than 20uv)between the capacitor discharge and log amp yesterday and it worked after lifting the diode. Today I tried capacitor direct to log amp and didn't see an offset problem.

I tied pin 1 of LOG114 to V- instead of common, forgot to change schematic. Not used so probably doesn't matter.

[Skippy]

No Spice, I have occasionally been curious about simulation, but never enough to bother trying it.

It seems practical problems like real-world noise limit how much of a range you need, so maybe trying to perfect the low-level input behaviour of this discrete amp is not productive?

[green]

I probably should point out I've no idea what to do with your zip / asc files, they are the circuit diagram in text form? So mention of V7 means nothing, as there was no V7 on the last circuit you posted, as far as I can see. But nevertheless, it looks like progress is being made.

Do you have LT spice? When I double click the asc. file it opens the schematic, then run opens scope screen.

[Skippy]

I probably should point out I've no idea what to do with your zip / asc files, they are the circuit diagram in text form? So mention of V7 means nothing, as there was no V7 on the last circuit you posted, as far as I can see. But nevertheless, it looks like progress is being made.

[green]

Yeah, it's a bit of a problem using the log-amp's input resistor as your capacitor discharge resistor, because it's a VIRTUAL ground, not the actual ground on the other end of the capacitor, so it's not going to fall to zero.
One possible alternative is to have a real discharge resistor across the cap, in addition to the resistor to the logamp input. If the discharge R was, say, 0.1 x the logamp input R, then it would dominate. Example R_discharge = 556 Ohms, R_input = 5K, gives an equivalent discharge R = 500 Ohms, just make the C value 10 times larger to compensate.

Tried it with log_3.zip. Disconnect signal input to R5 and connect R5 to common. Set V7 to .002volts. Setting V6 to .402volts adjusted offset when I tried. Remove common and connect R5 input back to signal. Looks like it doesn't cancel offset with capacitor discharge, changed 5u to 50u and added 500 ohms across capacitor.

[Skippy]

Yeah, it's a bit of a problem using the log-amp's input resistor as your capacitor discharge resistor, because it's a VIRTUAL ground, not the actual ground on the other end of the capacitor, so it's not going to fall to zero.
One possible alternative is to have a real discharge resistor across the cap, in addition to the resistor to the logamp input. If the discharge R was, say, 0.1 x the logamp input R, then it would dominate. Example R_discharge = 556 Ohms, R_input = 5K, gives an equivalent discharge R = 500 Ohms, just make the C value 10 times larger to compensate.

[green]

Yes, log-cal is what I'm referring to. I'm trying to work out a solution to the output voltage error at low input voltages (that causes the deviation from straight-line at 330msec onwards). You don't think it's a slow-response speed issue, so that leaves input offset error. I'm attempting to work out what you can adjust in the circuit to compensate for this. Fine-tuning V3 to vary the imbalance between the collector currents of the two transistors should allow the log output to be adjusted so it's a true straight-line.

You don't think it's a slow-response speed issue, so that leaves input offset error. I based that statement on the fact the capacitor discharge curve is straight until -.4volts. My PI amplifier noise limits the decay to about -.2volts so I was thinking speed wasn't the problem, might not be correct if offset cancels speed problem above -.2volts.

I'll to try to add the op amp between the capacitor discharge and log amp and see if I can zero it to less than 20uvolts. Then adjusting V6 should be the same with capacitor discharge and PI pre amp.

[green]

Yes, log-cal is what I'm referring to. I'm trying to work out a solution to the output voltage error at low input voltages (that causes the deviation from straight-line at 330msec onwards). You don't think it's a slow-response speed issue, so that leaves input offset error. I'm attempting to work out what you can adjust in the circuit to compensate for this. Fine-tuning V3 to vary the imbalance between the collector currents of the two transistors should allow the log output to be adjusted so it's a true straight-line.

Been playing with the problem. Added .002v offset to +input of log amplifier(log_3 and4.zip). Adjusting V6 straightens decay slope, both examples. Problem is, not the same setting for each example. Tried capacitor discharge into input resistor for checking response so I didn't have to worry about amplifier offset between capacitor and log amplifier. The input voltage is about 200uv at 330usec. Not seeing a good way to test decay response.

[Skippy]

Yes, log-cal is what I'm referring to. I'm trying to work out a solution to the output voltage error at low input voltages (that causes the deviation from straight-line at 330msec onwards). You don't think it's a slow-response speed issue, so that leaves input offset error. I'm attempting to work out what you can adjust in the circuit to compensate for this. Fine-tuning V3 to vary the imbalance between the collector currents of the two transistors should allow the log output to be adjusted so it's a true straight-line.

[green]

I think I was a bit clumsy with my suggestions about fine-tuning V3. I've done some rough calculations, and adjusting it by less than 1 mV is all that's required, I'm pretty sure you need to reduce V3, though it should be obvious if you've got it the wrong way. A figure of 1 mV is within the range you may expect for an opamp circuit; input offset voltages, bias currents, will be enough to skew things.

Are you looking at log cal.png? V3 sets zero volts at logout. Log out is zero volts when R5 current=R3 current. V6 is just an offset adjustment set to zero and not needed. Maybe I'm miss reading your comments or I'm looking at it wrong.

[Skippy]

I think I was a bit clumsy with my suggestions about fine-tuning V3. I've done some rough calculations, and adjusting it by less than 1 mV is all that's required, I'm pretty sure you need to reduce V3, though it should be obvious if you've got it the wrong way. A figure of 1 mV is within the range you may expect for an opamp circuit; input offset voltages, bias currents, will be enough to skew things.

[Skippy]

You should run your LOG114 at higher input currents, I'm guessing if you exceed 1 mA, you're not harming anything, you're just not getting proper performance, such as non-log behaviour, thermal issues, voltages hitting the power rail limits.

Regarding the discrete transistor / opamp model, I presume the two bias voltages V3 and V6 are supposed to 'match' each other, in terms of the current flowing into the two virtual grounds. Is this the case? Are they set at a 2: 1 ratio, such as V3 = 2 Volt, V6 = 1 Volt ? If so, you can tweek one of the voltages to adjust the 'zero input' behaviour. Changing V3 from 2V to 2.05V or 1.95V, for example.

Another experiment would be to change the two transistors to type BC337 (from 2N3904). These are higher-current devices with a lower r_bb base resistance, and they may be closer to the ideal.

[green]

My thought for checking decay slope. The dashed line is the calculated slope. The input on the LOG114 is 10k instead of 5k in the picture. Use 100p capacitor for 1usec TC, 330p for 3.3usec TC and 1n for 10usec TC.

Capacitor discharge into LOG114. Use log cal.png for reference. V1_coil driver command, swings +-2.5 volts from common. R1_10k. D1_1N4148. C1_100p, 330p or 1n. R5_10k. LOG114 replaces spice log amp. Probably would be better if R1 was a lower resistance.

Log amp circuits that I have seen have a much lower input resistor that you have. 100 - 500 ohms is common.

Eric.

LOG114 is rated for 1ma input current, so I could lower the input resistor from 10k to 2.5k.

I think it's either speed or the no target signal being not quite zero early in the decay like you suggested. Looks like speed isn't the problem.

[Ferric Toes]

I just thought I would run a plot for the silver quarter and clad quarter and here is the result. The top trace is for the two quarters and there is little difference. The midde trace for comparison is a US copper penny. The third trace is a US Cent.
Ignore the rulers and figures as I did not cancel them, and the graph is 500uS full scale rather than 1000uS in the previous ones. The quarters have not yet reached zero in this plot.



Eric.