PLL driven power oscillator with f-to-V conversion

[waltr]

Yep, typical "cross-over distortion".
Read about how to eliminate this in audio push-pull driver circuits- there is a lot of info.

Simple fix that might work is add diodes in series with R2 & R3 to the VCO out drive. The diode compensate for the transistor's Emiter diode drop is is where the distortion is coming from.
However, it also seems you have the transistor in the wrong places. The npn should be on top and the pnp on the bottom. This puts their emitters together and the diode ensure one of the transistor is always conducting. Again look up audio push-pull amps.

Interesting idea so keep us posted.

[Teleno]

The objectives of this circuit are:

(a) to provide an oscillator that works with a 5V power supply but can oscillate at a relative high peak voltage of 40V,

(b) to track tiny changes in frequency by converting them to a voltage signal with high gain.

The high voltage oscillation makes the tank very sensitive to targets (when measured by changes in amplitude). The high voltage is achieved by using low values of C and high values of L. Driving the tank from the ground side allows the use of low voltage transistors.

The heart of the project is the (in)famous CD4046 PLL. If the Phase Comparator 1 is used, when the chip's center frequency (fo) is the same as the tank's resonance frequency the voltage at the VCOin pin (triangle wave) dances around Vcc/2 with a 50% duty cycle. The VCO signal is then in quadrature with the input signal from the oscillator, which when buffered, is what we need to drive the transistors of the half-bridge.

When the VCO and the input signals are locked there's still a fixed phase error that causes switching artifacts at the transistors. An RC network between the VCO and the comparator's input introduces a compensation delay so that the transistors are switched on and off at the exact moment that the current in the coil crosses zero.

The PLL is configured with high R1 and low R2, which provides a narrow frequency locking range, and therefore large excursions of the control voltage VCOin for small changes in the tank frequency, which can form a base for target discrimination.





Now the million $$$ question: How to get rid of the steps at the peak of the signal? (V(osc) in green)




They are caused by the cross-over current peaks at Q5 and Q6 (red and blue traces) not being equal. The difference charges the capacitor C1 of the tank (peaks in the blue trace), causing the sudden voltage steps in the signal.

Any ideas on how to tame them?

You can play with the simulation file attached. It contains a good model of CD4046B, use the inc. command to include it in your sims.
I will also share the equations to work with the CD4046:

fo = (Io + Ic) / (2 x C x (Vcc/2 + 0.813))

where:

Io = (Vcc - 1.14) / R2
Ic = 0.695 / R1

The ratio Io / (Io + Ic) gives the locking range in % of fo.