Single capacitor integrator switch placement

[Cazavor]

No, in fact I don't use a pot at all.

You're right as always Carl. When using precision components, such as 1% resistors or better, a potentiometer is not needed at all.

My problem turned out to be a very simple mechanical one. Namely the BNC plug and socket I bought from my local electronics shop made only an intermittent connection at best. I did not suspect that all since those parts were brand new.

Some people on the internet are saying that 50 and 75 ohm coax connectors have different parameters while others swear that coax connectors are all the same. I don't know what to think about that.

For now, I just did away with all the connector stuff and made a direct coax connection from the coil to the control box. Works perfectly.

[Carl-NC]

I think its due to not precise enough EF balance. Is it normal to need a multiturn pot for this?

No, in fact I don't use a pot at all.

[Cazavor]

I built what is essentially HH2 with 1C integrator. Using a 100R 1-turn pot for balance I can get the detector to reject a weak 20x3 mm ceramic disk magnet, but the pot needs to be in a very specific position approximately in the middle for that. A large 50mm toroid magnet from speaker is only slightly rejected. The detector works fine while static, but when I move it the output goes all over the place. Tested outside away from metal. I do live 200 m from a 110 kV power line.

I think its due to not precise enough EF balance. Is it normal to need a multiturn pot for this?

[green]

Been playing with spice and Excel. I remember measuring integrator out noise with a 10us and 100us sample with my bench circuit. 100us sample has 10 times the gain but about 3 times the amplitude increase. Longer sample helped reduce the noise. Tried integrating white noise with spice, noise didn't decrease with longer samples. HP filtered white noise at 50kHz and tried again, longer samples did reduce the noise. Guessing the coil was picking up higher frequency noise with the bench circuit.

[green]

The original differential integrator required two matched jfets and two matched capacitors. Both took time to match, but even when done and with a preset to adjust the resistive balance, it was acceptable but not the best. Theoretically, this type of integrator always has an error component due the mismatch of the opamp input impedances.

The sample hold type with the additional inverting opamp was better in that there was no droop in the hold period, and it had the facility to adjust the overall TC by means of altering the feedback resistor in the second stage. It still required matching capacitors and the balance preset for input resistances.

The latest integrator uses only one capacitor, so there is no matching, which to me is a great benefit. Using better gates with considerably lower 'On' resistance than jfets should mean that matching these goes out the window. I am only using jfets because I am doing an upgrade on a pcb that has them and there is no room to fit other types such Cmos.

Performancewise, there is little to choose, but not having to match capacitors is to me, a big bonus. Also the notch in the response is much more pronounced when the resistive part is properly balanced and input impedances are the same. It would be interesting to put some component tolerances into your simulation if that is possible; particularly for the two capacitor integrators.

Eric.

Agree. I'm comparing the same circuit. https://www.geotech1.com/forums/atta...1&d=1592439607 switch wiring is different(fdbk resistor location) and fdbk resistor(R3) is different to adjust gain the same.

[Ferric Toes]

Don't see why either integrator would be better than the other if gain and response are the same and not doing ground balance. Normal integrator can do GB by making the ground sample longer than the target sample or ground sample samples an extra stage of amplification with target and ground sample times being the same. Eric's integrator can do GB with the second option only. Been using first option with normal integrator, wondering if second option might be better. Has anyone compared the two methods to see which is better? If comparing which integrator is better, do you want changing sample time to change integrator TC(response)? If yes then Eric's is better.

The original differential integrator required two matched jfets and two matched capacitors. Both took time to match, but even when done and with a preset to adjust the resistive balance, it was acceptable but not the best. Theoretically, this type of integrator always has an error component due the mismatch of the opamp input impedances.

The sample hold type with the additional inverting opamp was better in that there was no droop in the hold period, and it had the facility to adjust the overall TC by means of altering the feedback resistor in the second stage. It still required matching capacitors and the balance preset for input resistances.

The latest integrator uses only one capacitor, so there is no matching, which to me is a great benefit. Using better gates with considerably lower 'On' resistance than jfets should mean that matching these goes out the window. I am only using jfets because I am doing an upgrade on a pcb that has them and there is no room to fit other types such Cmos.

Performancewise, there is little to choose, but not having to match capacitors is to me, a big bonus. Also the notch in the response is much more pronounced when the resistive part is properly balanced and input impedances are the same. It would be interesting to put some component tolerances into your simulation if that is possible; particularly for the two capacitor integrators.

Eric.

[green]

I think Eric's intergrator may shine in a ground balance set up. I thought I read somewhere the gain of the ground balance stage must compensate.

Don't see why either integrator would be better than the other if gain and response are the same and not doing ground balance. Normal integrator can do GB by making the ground sample longer than the target sample or ground sample samples an extra stage of amplification with target and ground sample times being the same. Eric's integrator can do GB with the second option only. Been using first option with normal integrator, wondering if second option might be better. Has anyone compared the two methods to see which is better? If comparing which integrator is better, do you want changing sample time to change integrator TC(response)? If yes then Eric's is better.

[dbanner]

Sorry I meant which version of integrator.

The circuit Qiaozhi has been simulating with ltspice.

[6666]

I was thinking of goldsan IV circuits. Been a while since I've looked at those.

Sorry I meant which version of integrator.

[dbanner]

Which version did you have in mind ?

I was thinking of goldsan IV circuits. Been a while since I've looked at those.

[6666]

I think Eric's intergrator may shine in a ground balance set up. I thought I read somewhere the gain of the ground balance stage must compensate.

Which version did you have in mind ?

[dbanner]

I think Eric's intergrator may shine in a ground balance set up. I thought I read somewhere the gain of the ground balance stage must compensate.

[green]

Wondering if Eric's integrator or normal 1C integrator would be better if both had same gain and time constant. I need to make a detector circuit for another project. Could make it easy to move the switch locations for either integrator. How to compare which is better? Use a quarter for target. Thinking wire for Eric's first, adjust sample time for best SNR. Wire normal, change Rfdbk to give same gain and time constant as Eric's. Compare SNR. Adjust sample time to see if SNR can be improved. Any thoughts?

[green]

I know nothing about metal detecting, just trying to learn something metal detectors. One benefit of this integrator is being able to change the filter response if coil size is changed. Example: response is adjusted for a 30cm coil, switch to a 15cm coil. Thinking response needs to be faster. Sample time needs to increase to make the response faster. Thinking increasing sample time is opposite of what I should do, maybe wrong?

[green]

Many Thanks, George, it makes things a lot clearer now. I didn't appreciated the fact that the resistor networks around each gate are effectively in parallel as both 2K2 resistors go to 0V (no signal) on the cross coupled inverter outputs, and which will reduce the gain to 5. Apologies to Green who was correct on this

The glitching looks terrible on the simulation, so I had a look with my analog 'scope. [ATTACH]50649[/ATTACH]. I presume the parasitic capacitance of the jfets are responsible. Anyway it is quickly damped and negligible compared to the sample width. As these glitches are synchronous with the pulses I expect that their effect is negligible. I will try a filter on the output to see what minimum is necessary to get rid of the ringing.

Eric.

R8*C2=22us works good with Qiaozhi's simulation