NEW !!! Full differential PI front end.

[Tinkerer]

Hi Tinkerer.
I use this method successfully. Samples of the prescaler counts the 6-12bit and counter 16bit driven by clock 2MHz.
As to what occurred indefinitely unexpected increases (EMI?).
I used repetition - 4x enough, the situation as the perfect fairy tale.
Total applied to the magnetometer - gradiometer with ATMega8 (ATMEL) and SD card through the RS 9600baud. It was enough for two results per second.
Now I'm learning, "PSoC" (Cypres), a similar system, controls the 8bit prescaler counter 16bit driven by clock 4MHz.
For now, no communication is sufficient for 100 results per second.
Best regards Chris

Hi Krzyszof,

Thank you for your comments.
I am not sure I understand all of it. The translator has twisted some meanings.

Is your magnetometer a Proton Precession Magnetometer? Proton
magnetometers run at a much lower pulse repetition rate than metal detectors.

It is also difficult to run a traditional PI-MD at 10A coil current at a high repetition rate.

The fact that it is possible to run a PI-MD at a rate of several thousand pulses per second at high coil currents, is what has me excited about the TEM TX method.

Tinkerer

[Tinkerer]

As I mentioned, I did a 10-bit sampler off the preamp, just to see what it would do. I did a boxcar average on 16 points for the target, then took that average and averaged it again 16x (effective 256x) for the "tracking" average. It worked surprisingly better that I expected. I was limited by the low-memory PIC I was using.

Your HH II, is a very good way to show how an analog PI detectors can be changed into a digital one.

At how many PPS are you running it in the example above?
How does the HH II compare with the HH I in sensitivity and depth?
Is the response faster? slower? the same?

I consider the HH I and the HH II the best designs for beginner metal detector builders.

Is there any chance you get time to work on the HH III?

Tinkerer

[Krzysztof]

Hi Tinkerer.
I use this method successfully. Samples of the prescaler counts the 6-12bit and counter 16bit driven by clock 2MHz.
As to what occurred indefinitely unexpected increases (EMI?).
I used repetition - 4x enough, the situation as the perfect fairy tale.
Total applied to the magnetometer - gradiometer with ATMega8 (ATMEL) and SD card through the RS 9600baud. It was enough for two results per second.
Now I'm learning, "PSoC" (Cypres), a similar system, controls the 8bit prescaler counter 16bit driven by clock 4MHz.
For now, no communication is sufficient for 100 results per second.
Best regards Chris

[Carl-NC]

As I mentioned, I did a 10-bit sampler off the preamp, just to see what it would do. I did a boxcar average on 16 points for the target, then took that average and averaged it again 16x (effective 256x) for the "tracking" average. It worked surprisingly better that I expected. I was limited by the low-memory PIC I was using.

[Tinkerer]

Integrating ADCs only integrate on a per-sample basis, not across multiple samples like a true sampling integrator. So you still don't get sample-to-sample filtering.

Be careful using sigma-delta. Most require oversampling which means you will be sampling continuously along the RX waveform, and the specific sample points you're really interested in will get buried. You can put a S&H in front of a SD-ADC but you will be limited to one sample point per ADC.

If you are looking at 1-3 sample points on the decay, I would recommend using sampling integrators as in a normal PI. If you want to look at 4 or more sample points, or you want to do some exotic filtering, then consider a high-res SAR ADC and a good micro. 16-18 bits with 1us resolution is easy.

- Carl

Thanks for the explanation, Carl,

I had a mis-conception about the meaning of oversampling.

I want to sample at 4 or 5 different times. Average each one of the samples over 3,000 to 10,000 readings and store the results. (running at 3,000PPS)

This is my ground sample.

Then I want to repeat the same operation, but with averaging only 50 to 100 readings for target search.
The difference between the two results, processed, should give me the target information.

I am trying to decide how much of the front end to keep in analog before digitizing. Less seems to be better, but I am still trying to wrap my mind around the dynamic range.

So much still to learn............

Tinkerer

[Carl-NC]

Integrating ADCs only integrate on a per-sample basis, not across multiple samples like a true sampling integrator. So you still don't get sample-to-sample filtering.

Be careful using sigma-delta. Most require oversampling which means you will be sampling continuously along the RX waveform, and the specific sample points you're really interested in will get buried. You can put a S&H in front of a SD-ADC but you will be limited to one sample point per ADC.

If you are looking at 1-3 sample points on the decay, I would recommend using sampling integrators as in a normal PI. If you want to look at 4 or more sample points, or you want to do some exotic filtering, then consider a high-res SAR ADC and a good micro. 16-18 bits with 1us resolution is easy.

- Carl

[Tinkerer]

Carl and Aziz,

many thanks for the explanations.

Looking at the Maxim application notes, I find the 100 conversions per second a bit slow.

The integrating ADC looks good for my planned design that uses large coils.

For small coils, 100 conversions per second would make a rather slow response. Do I get that right?
Considering a sweep speed of 100cm/second, it would mean one conversion per 1cm distance traveled by the coil, not considering any additional signal processing time.

For large coils, the sweep speed will be at 50cm/second or less.
With the large coil, a response time of 5cm, or 100ms is acceptable.

Using the TEM method we can run a large coil at 3000 PPS with 10 Amps coil current. So we can do some oversampling. A Sigma/Delta ADC could also be used.

Does this make sense?

Tinkerer

[Aziz]

Hi Moodz,

have a look into integrating ADC's:

http://www.maxim-ic.com/app-notes/index.mvp/id/1041

http://en.wikipedia.org/wiki/Integrating_ADC

http://www.allaboutcircuits.com/vol_4/chpt_13/8.html

The integrating ADC eliminates most of the noise during the conversion operation.

Aziz

[Aziz]

Hi Tinkerer,

I can add some more to Carls post.

The LF398 is just a gated voltage follower (gain=1). Where as a true integrator is like a transconductance amplifier. The integration is made via voltage to current conversion and the current charges a capacitor (makes the real integration). Op-amp circuits in inverting configuration are typical transconductance amplifiers (I-V conversion). So an integrator circuit is typically in such an inverting op-amp configuration.

Therefore the LF398 can not make the integration. In your circuit, the high series resistor to the holding capacitor forms a LPF but it does not integrate. It also increases the settling time of the S&H amplifier.

One can make an integrator, which also has a S&H capability. It should be called integrate & hold in this case of course.

Good integrators should have a gated differential input and a clear (reset) possibility. As the signal should be fed in differential manner, any leakage input currents will chancel each other. And one can select the polarity of the integration (doing signal addition, subtraction) . And if both inputs were disabled, it will hold the integration output until it is cleared.

Integrators in PI's greatly reduce high frequency noise.

Aziz

[Carl-NC]

Sampling into an ADC has some advantages. First, you get the full instantaneous amplitude of the sample instead of a time-integrated amplitude. Second, an integrator limits your LPF to a simple exponential decay, whereas an ADC approach lets you try out radically different digital filter algorithms. Third, the ADC makes it really easy to run multiple sample channels without building a lot of analog integrator channels.

The drawback is you need an ADC that is fast enough and with enough resolution. I've made a workable PI detector with only 10 bits right off the preamp. 16-18 bits is now very reasonable.

No, the S&H approach does not replicate the LPF of the integrator. The extra series R with CH slows down each individual sample which will LPF that particular sample, but there is no sample-to-sample integration filtering, which is where you get noise reduction.

- Carl

[Tinkerer]

Hi Moodz,

I would suggest to use integrated samples over a time window rather than just sampling the signal values. Integrators have an inherent low pass filter characteristics, which reduce high frequency noise automatically. The output of the integrators should be sampled instead.

The FPGA is well designed to implement several integrating ADC's. Let's assume, your conversion time is 1 ms and your ADC clock is running at 200 MHz.
For one ADC cycle there will be 200 000 clocks
n ADC bits = ld (200 000) = 17.6 bits (max. ADC resolution)


So you would need a precision current source (voltage ramp generator at charging capacitor), a fast comparator and a 18-20 bit counter each ADC channel. The µC/DSP could read the channels and process it.

You can get rid of the external ADC. The FPGA could do it with ease.
Aziz

Aziz,

I have been using the circuit below (found on the datasheet) for the S&H of the TINKERERS IB-PI. I wonder how it compares with an ordinary Integrator.
Would you be so kind and give your opinion?

Tinkerer

[moodz]

Hi Aziz ... thanks for that very good idea ... the FPGA input can digitise analogue signals with minimal external components like this ....

WP-Creating_An_ADC_Using_FPGA_Resources.pdf


moodz

[Aziz]

Hi Moodz,

I would suggest to use integrated samples over a time window rather than just sampling the signal values. Integrators have an inherent low pass filter characteristics, which reduce high frequency noise automatically. The output of the integrators should be sampled instead.

The FPGA is well designed to implement several integrating ADC's. Let's assume, your conversion time is 1 ms and your ADC clock is running at 200 MHz.
For one ADC cycle there will be 200 000 clocks
n ADC bits = ld (200 000) = 17.6 bits (max. ADC resolution)


So you would need a precision current source (voltage ramp generator at charging capacitor), a fast comparator and a 18-20 bit counter each ADC channel. The µC/DSP could read the channels and process it.

You can get rid of the external ADC. The FPGA could do it with ease.
Aziz

[moodz]

FPGA update

There is really only one way to decide where along the timeline of the cycle to place the sampling spots.
You have to sample every part of the cycle, see what the target and ground response is at each spot, then chose the few best spots, that is the spots that give you the most reliable information about the target and the ground, to take your samples.
You need to do this initial testing, using every possible target size and metal and every possible ground effect. Quite a lengthy procedure really.

It is surprising how moving a sample timing spot by just one or 2 us, can change the effectiveness of the sample.

Then you invert, add, subtract, divide or multiply specific sample groups, to eliminate ground effects, enhance FE recognition or rejection and generally enhance the response of the most desired targets.

I would be willing to do some of these test series for you, but I need to have and use your exact setup, to make sure the results fit precisely your system and methods.

Any change in coil, TX power and duration, front-end circuit, etc. will change the output. However, with the great resources of the FPGA, these changes can be compensated, as long as you know exactly how the desired responses need to be.

Tinkerer

Ok I will make up 4 sample points for each pulse period. There will be two types of pulse period. One with a single pulse ( fully variable ) and a doublet or triplet pulse period ( fully variable )
This will be upto 8 sample points in total across both pulse periods.
The sample controls will be a 16 bit value to set sample delay ( 10 ns resolution ) and sample duration or ADC count ( number of ADC values to sample.)

moodz

[Tinkerer]

Changed the pulse generator back to 100 Mhz clock ... step size is 10 ns .. 0 to 65535 ( 16 bit control ) or 0 to 655.35 us in .01 us steps.

The sample clock is 1.3 Mhz and the pulse repetition is 196 us or 5.098 Khz .... pretty high for a PI but lots of samples = lots of sensitivity.

Now the question is how many sample points ????

1 sample during transmit.
1 early sample just after fly back
1 mid sample 50 to 100 us
1 late sample at 196 us

How to process ???

moodz

There is really only one way to decide where along the timeline of the cycle to place the sampling spots.
You have to sample every part of the cycle, see what the target and ground response is at each spot, then chose the few best spots, that is the spots that give you the most reliable information about the target and the ground, to take your samples.
You need to do this initial testing, using every possible target size and metal and every possible ground effect. Quite a lengthy procedure really.

It is surprising how moving a sample timing spot by just one or 2 us, can change the effectiveness of the sample.

Then you invert, add, subtract, divide or multiply specific sample groups, to eliminate ground effects, enhance FE recognition or rejection and generally enhance the response of the most desired targets.

I would be willing to do some of these test series for you, but I need to have and use your exact setup, to make sure the results fit precisely your system and methods.

Any change in coil, TX power and duration, front-end circuit, etc. will change the output. However, with the great resources of the FPGA, these changes can be compensated, as long as you know exactly how the desired responses need to be.

Tinkerer