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  • simonbaker
    replied
    Originally posted by Aziz View Post
    Hi Simonbaker,

    this is part 2: (I had to shorten my first post due to a visit)

    Of course, the coil current I(L2) have to reach the I0/2. But this is more obvious, if transmitter coil is fully decoupled from the bifilar coil (transformer principle, seperate mono TX, bifilar RX).

    During the build up of the flyback, there will be some resistive loss and the coil current does not reach fully I0/2.

    But the coil current is not relevant. What counts is the first derivate of it (dI/dt).

    Aziz
    Thanks Aziz, I will study your comments.

    First, I was not sure if my LTSpice simulation is physically accurate - I gather you feel it does represent reality, correct?

    Second, my purpose with the sim is to identify what we really are gaining with the bifilar / center-tapped coil. Are we gaining any magnetic field advantage, or is it basically the same as a single coil with same amount of wire? I understand (I think) the benefits of the differential design.

    Third, some previous discussion suggested that the current in the two coils became instantaneously identical at MOSFET shutoff. However, my LTSpice sim indicates that the current briefly grows in one coil while decreasing in the other, and the difference is made up for by current coming through the diode from V+. When the two coil currents become equal, the sim shows the diode current stops, and both coil currents (really the same current) decaying at a slower exponential rate. I'm not clear whether that initial transition period is physically realistic, or a Spice artifact.

    I'll try to look over your equations, probably some answers in there.

    Regards,

    -SB

    Leave a comment:


  • Aziz
    replied
    Hi Simonbaker,

    this is part 2: (I had to shorten my first post due to a visit)

    Of course, the coil current I(L2) have to reach the I0/2. But this is more obvious, if transmitter coil is fully decoupled from the bifilar coil (transformer principle, seperate mono TX, bifilar RX).

    During the build up of the flyback, there will be some resistive loss and the coil current does not reach fully I0/2.

    But the coil current is not relevant. What counts is the first derivate of it (dI/dt).

    Aziz

    Leave a comment:


  • moodz
    replied
    Originally posted by moodz View Post
    Thanks ... I am not sure if releasing the source code is a good idea just yet .... It is still changing and needs to live in a proper project page. Releasing source code in a forum is asking for trouble ( never ending questions like ... how do I compile this ? ... and what does this code do ? Im a newby can you explain from beginning ? etc etc etc )
    I have been there before . I may just provide it programmed into boards on ebay.

    The front ends are the same as your conventional PI's .... I will publish this however .. must finish release v1.000 coding first

    moodz.

    OK I have go another cunning plan for releasing the source code.

    It goes like this .... lets call it the Contributory Licence Scheme .... the code itself will be GPL or LGPL as some of the cores I use already fall under this licence ... like the CPU core for instance. The contributory licence is a wrapper around the GPL / LGPL and is set out thus ...

    The Contributory Licence means you have to contribute to the project in some way. How can you do this ? I dont mean money ( though that is an option BTW) .

    Anyone given access to the code for ANY of the following reasons will be deemed an Accredited Developer ( level 1 or 2 ) or Developer Friend ( see clause 3 ).


    1. You can contribute by making changes or improvements to the code that in some way are beneficial to functionality or utility of the code. For this clause to be fulfilled you will have to verify in some way to the project maintainers that you at least have the basic development tools as specified by the project maintainers. ( till more people on board .. that is me )

    2. In other cases the source code may be used as a learning resource or for using parts of it to do something entirely different. So you contribute by asking questions about the code, providing new ideas maybe suggesting stuff that no-one else thought of. You will still have to fulfill the development requirements of clause 1 above and verify to us the maintainers that you can operate the basic development environment even if you cant understand the code you are looking at. ( well you are supposed to be learning something here OK ? )

    3. You can contribute by providing money or material assistance to other developers. Some of the accredited developers have the skills and ideas but lack the means to access equipment or sufficient parts or funds to participate fully in the development.
    Or say you want a particular feature modified or added you can make a donation for the effort involved. Even if you use the code commercially you could make a donation in appreciation of the effort that the developers have already 'donated'.
    In this case you get access to the source code as an indication that your contribution is actually being used in a productive way.

    -------------------------------------------------------------------------------------------------------------------------

    To become an Accredited Developer ( level 1 or 2 ) you will have to provide evidence that you have the correct development environment to the project maintainers. So you will need at least one of the supported hardware platforms and have the correct development software installed. ( this will actually avoid alot of questions later on )

    The required hardware is Spartan S3E500 starter kit. ( other boards soon )

    The required developer environment is .. Webpack ISE 12.1 from Xilinx

    Linux or Cygwin environment to run the C compiler for MIPS

    Once you have these set up correctly just request by way of email, PM etc for developer accreditation. The project maintainers will send you a file and a relatively simple task. If you can email back the message that appears on the LCD screen of the hardware board then you will be made an Accredited Developer and the maintained source code base is yours..... simple.

    Clause 3 is fairly obvious. This will make you a Developer Friend.

    moodz.

    Leave a comment:


  • Tinkerer
    replied
    Originally posted by doncaffe View Post






    The Geotech forum definitely need good mathematic equation editor !!!
    doncaffe,

    thanks for the explanation.
    I am a bit confused though. It is one thing to look at the Mosfet drive pulse and another thing to look at the coil magnetic field, which depends on the coil current, not the voltage.
    It is the coil current that makes the magnetic field that generates the eddy currents in the target.

    So how can I produce a coil current wave form like 5/T with a coil inductance of 300uH?

    The TEM TX METHOD is giving a good variety of frequency response as I am showing in the thread:
    General tech discussions on all types of metal detectors: VLF, 2-box, BFO, off-resonance, PLL, etc. Questions, ideas, and anything else that moves you.


    I think that Moodz's FPGA will be the ideal platform to implement the TEM TX METHOD and will make it possible to extract a wealth of information about the targets from the response signal.

    Tinkerer

    Leave a comment:


  • WM6
    replied
    Originally posted by moodz View Post
    Thanks ... I am not sure if releasing the source code is a good idea just yet .... It is still changing and needs to live in a proper project page. Releasing source code in a forum is asking for trouble ( never ending questions like ... how do I compile this ? ... and what does this code do ? Im a newby can you explain from beginning ? etc etc etc )
    I have been there before . I may just provide it programmed into boards on ebay.

    The front ends are the same as your conventional PI's .... I will publish this however .. must finish release v1.000 coding first

    moodz.
    I can understand.

    I am not sure that eBay can exclude all possible support?

    But if you can provided good building guide for complete project, many headaches can be avoided for you and for buyers.

    I suppose that whole project will be published here to assess and facilitate the purchase of programed FPGA (and maybe some others part/stages too) decisions?

    Leave a comment:


  • moodz
    replied
    Originally posted by Aziz View Post
    Hi Don,

    I am a bit confused by your naming convention:
    square wave and rectangular wave

    What do you mean by that?

    Aziz
    Is Don referring to pulse trains like Minelab PIs.??

    Leave a comment:


  • moodz
    replied
    Originally posted by WM6 View Post
    Excellent! Thanks moodz.

    How to get last source code?

    What FPGA periferial circuits to use/build to get usable detector (which frontend etc.)?
    Thanks ... I am not sure if releasing the source code is a good idea just yet .... It is still changing and needs to live in a proper project page. Releasing source code in a forum is asking for trouble ( never ending questions like ... how do I compile this ? ... and what does this code do ? Im a newby can you explain from beginning ? etc etc etc )
    I have been there before . I may just provide it programmed into boards on ebay.

    The front ends are the same as your conventional PI's .... I will publish this however .. must finish release v1.000 coding first

    moodz.

    Leave a comment:


  • Aziz
    replied
    Hi Simonbaker,

    Originally posted by simonbaker View Post
    Continued from prev post... More interesting graph showing sum of currents in coils too. Derivitive of sum gives induced current in target???? (of course this is without MOSFET breakdown).

    -SB
    if you have only one coil, the current will remain at last current at t-off (switch-off time) and then starts to diminish from this point.

    On the bifilar type coil, we have at switch-off period two coupled coils.
    The total inductance L will be:
    Ltot = L1+L2 + M12 + M21
    M12 = M21 = k*sqrt(L1*L2), (mutual inductances)
    where k=1, the coupling coefficient (sharing the same coil flux area)
    So, Ltot = L1+L2 + 2*sqrt(L1*L2)

    The dB/dt applies to both coils L1, L2 at switch-off. From the point of energy balance, the output energy may not be higher than the input energy. The intregral E=U(t)*I(t)*dt (delivered energy from the coil) for the period of switch-off time (until next switch-on time) must be equal to E=0.5*L*(I0)² (emitted magnetic field energy at switch-off time), (I0=switch-off coil current).

    TX period: E=0.5*L*(I0)², L=L2 in your example

    RX period: E=0.5*Ltot*(Irx)², L1=L2, Ltot=4*L2,

    Solving the equation:
    0.5*L2*(I0)² = 0.5*4*L2*(Irx)²
    (I0)²=4*(Irx)²
    (Irx)²=(I0)²/4
    Irx = I0/2

    So the current in the receive period must be switch-off current I0 /2 and starts then to diminish from this value.
    Q.E.D.

    Aziz

    Leave a comment:


  • moodz
    replied
    ... and furthermore .... I'm on a run here .... as some of you may have guessed already ... it is very simple to make an arbitrary waveform generator in the FPGA instead of the pulse generator ... output PWM or play out of the DAC ... to a power amp to drive the coil ... and you can then build any type of metal detector .... VLF, BFO ... triangular waves, sine waves, psuedo random etc etc.
    Most analogue circuits can be all done in DSP.

    moodz

    Leave a comment:


  • WM6
    replied
    Originally posted by moodz View Post
    ...

    11. All of the above is coded inside the FPGA, tested and works and I have only used up 59% of the resources of a cheap ( $20 ) FPGA.

    moodz.
    Excellent! Thanks moodz.

    How to get last source code?

    What FPGA periferial circuits to use/build to get usable detector (which frontend etc.)?

    Leave a comment:


  • moodz
    replied
    Originally posted by moodz View Post
    Well thanks Don .... I do appreciate your reply ...actually I am not sure yet what will eventually deliver the descriminating PI detector .... Maybe it will be FFT ... if there was a recipe to do this I would just build one and save my time and money.

    However there is no project of that will suit as test bed to test all possible detector theory. ... This is a problem ...everyone talks about theories on this forum ... but there is no general purpose test bed.

    The nearest we have to a test bed is LTspice and maybe breadboard and Oscilloscope.

    All I am trying to do with the FPGA is create a container with all the tools you need to test out ideas that can be expressed in mathematics ( or DSP if you like ).
    So I have the following things in the chip.
    and the following things are ( because I accidently pressed submit too early ... he he )

    1. One or more pulse generators that can be numerically controlled ( duty cycle and frequency ). Obviously need this to control the MOSFET switching. However my initial design will be very similiar to an older minelab.

    2. One or more ADC drivers to get analogue data into the system.

    3. One or more DAC drivers to generate analogue signals either for feed back to amplifier front end, coil balancing, meters .... whatever.

    3. One or more rotary knob controller so you have user controls.

    4. A sound synthesiser for user alerts and maybe music during lunch breaks.

    5. one or more LCD driver so you can display stuff . ( 2 x 16 char currently )

    6. Multichannel VGA digital oscilloscope so you can see signals not only what the ADC captures but also results of DSP computations. Also very useful for checking coil performance etc. This single feature alone is the most useful to have as you can see if your design works or not ... in the field.

    7. VGA also displays text console so you dump lots of info about things that wont fit on LCD.

    8. serial port so you can connect to computer. On the larger Xilinx Board there is ethernet and more RAM / Flash also.

    9. A 32 bit MIPS compatible RISC processor on the FPGA for user code. ( the fast DSP is done in FPGA though ... more efficient) This does the menus, reads the rotary knob values, controls the displays and maybe does the high level descrimination.

    10. DSP code blocks that can switched into the signal chain ...

    11. All of the above is coded inside the FPGA, tested and works and I have only used up 59% of the resources of a cheap ( $20 ) FPGA.

    moodz.

    Leave a comment:


  • Aziz
    replied
    Hi Don,

    I am a bit confused by your naming convention:
    square wave and rectangular wave

    What do you mean by that?

    Aziz

    Leave a comment:


  • moodz
    replied
    Well thanks Don .... I do appreciate your reply ...actually I am not sure yet what will eventually deliver the descriminating PI detector .... Maybe it will be FFT ... if there was a recipe to do this I would just build one and save my time and money.

    However there is no project of that will suit as test bed to test all possible detector theory. ... This is a problem ...everyone talks about theories on this board ... but there is no general purpose test bed.

    The nearest we have to a test bed is LTspice and maybe breadboard and Oscilloscope.

    All I am trying to do with the FPGA is create a container with all the tools you need to test out ideas that can be expressed in mathematics ( or DSP if you like ).
    So I have the following things in the chip.

    Leave a comment:


  • Qiaozhi
    replied
    Originally posted by doncaffe View Post
    The Geotech forum definitely need good mathematic equation editor !!!
    Try using the latex editor ->

    Leave a comment:


  • doncaffe
    replied






    The Geotech forum definitely need good mathematic equation editor !!!

    Leave a comment:

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