Announcement

Collapse
No announcement yet.

Announcement

Collapse
No announcement yet.

AMX Digital

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • Olly
    replied
    Originally posted by Carl-NC View Post
    Ivica, you're asking all the right questions. I'm a Big Fan of illustrations so let's dive in (again, all this belongs in the Concept discussion, but we'll go with the flow). Here is a multi-pulse TX using 2 rates:

    Click image for larger version Name:	image.png Views:	0 Size:	4.6 KB ID:	409115
    I used 25kHz because Tony suggested it, and 5kHz because it gives me a familiar 100us TX width. If you transmit only 25kHz then you are stuck with trying to squeeze a GB sample in that 20us window which is tough. Plus, your GB has a dreaded target hole. In this example I used (5) pulses of 25k per (1) pulse of 5k; in reality we might instead use 4:1 or 8:1 just to make scaling in DSP a little easier. You can also change the ratio to implement variable frequency weighting.

    Let's suppose we use analog demods. Here is my first guess as to what to try:

    Click image for larger version Name:	image.png Views:	0 Size:	10.3 KB ID:	409116

    Boy, I love being able to just <paste> these images! So I have 4 RX channels: (1) for 25kHz and (3) for 5kHz. Maybe we could squeeze in another sample for the 25kHz pulse but I doubt it would do any good. GB is achieved with a combination of RX25, RX5a, and probably RX5b. Discrimination might be achievable with RX5a,RX5b,and RX5c.

    The clocks above are demod clocks. The demods are integrating the results so the ADC does not need to run this fast. You can sample the demods every 400us (2.5kHz) or even slower if you like. Let's say we sample at 2.5kHz. The ADC creates a DataReady pulse which triggers a micro interrupt. The micro reads the ADC and DMA's the result. So far this takes nearly zero overhead. But you don't want to run a processing loop at 400us unless you are using a really fast micro. So instead, you pile up the samples (either in a circular buffer or by just summing the data) and say, every 5ms, you send all the data to the DSP task. (Most metal detectors run a processing loop of 5ms.) A processing loop of 5ms on a micro running at 32MHz gives you 160,000 single-cycle instructions to work with.

    So now you have a hard example of an analog demod solution: 4 demod channels, a 16-18 bit 4-channel simultaneous sampling ADC running at 2.5kHz, and not-too-aggressive micro.

    Let's say we want to use direct sampling on the above TX waveform. I will take a guess and say I want 4 samples for every 20us pulse. This now sets my ADC sample rate at 200kHz, and it needs to be 24 bits. You will be hard-pressed to grab data that fast in the same micro as the one doing the DSP. So maybe you need a data capture micro that simply sums up the data and eventually feeds it to the DSP processor at the 5ms loop rate. Or maybe you need a really fast M7 micro. Or maybe I only get data at 100kHz or, worse, 50kHz. Note that you probably don't need 20 samples per 5kHz pulse, but it's way easier to run the ADC at a constant rate and just toss unwanted samples.

    Before I hit the Post button, notice that the TX waveform has a positive 100us pulse every 400us. The TDI/Goldscan has a 100us pulse every 320us. So just the response from the single 100us positive pulse should be somewhat comparable to the TDI. But we also get a second (negative) 100us pulse, and 10 (!) 20us pulses in the same time frame. So this thing should hands-down beat a TDI on small gold.
    Hi Carl

    I've been re-visiting this post to get a better understanding of the various virtual channels proposed and how to go about realising them with direct sampling.

    I'm happy with the locations of the RX25 & RX5a + and - slots, but am not so sure about the RX5b & c slots, let me try explain: -

    X5b+ and RX5c+ occur in a period where the previous positive going transition of the TX clock occurred after a 20uSec active period, whereas RX5b- and RX5c- occur in a period where the previous negative going transition occurred after a 100uSec active period. Is it possible in this case that the + and - samples may not be equal and opposite to each other (barring EFE effects) ?

    Regards,
    Olly

    Leave a comment:


  • Olly
    replied
    Originally posted by Willy Bayot View Post

    Yes, the first phase of capture is made using DMA and feeding the FIFO, it is continous without any synch with the pulses.
    The second capture phase (made in parallel by the main program loop) is made by synchronizing the reading in the FIFO with the start of each period and accumulating the FIFO values into the slots of another array. The end result is an array made of as many slots as necessary to cover the whole pulse period. Example : period of 200µsec captured @ 1Msps generates 200 slots.
    Each slot is the integration of a number of consecutive periods (e.g. integration of 20 consecutive periods gives one net series of accumulated slots every 4msec).
    Next, the real windowing is defined by selecting the starting slot and width of each digital integration window and they are accumulated in as many virtual demodulators.
    Finally, the demodulators are used for the DSP and reporting.
    Because I have one laying around I intend to use one of the CMOD-A7 FPGA modules to do my experimental work with. To this end I've started writing some Verilog code to drive the ADC and capture the 1uSec samples into Fifos. I have a question regarding the accumulation of data for the 4mSec processing loop. Do you envisage this merely being the accumulation of each slot over the 4mSec period which is then reset at the start of every period or would a rolling average of each slot be a more desirable solution?

    Regards,
    Olly

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by Carl View Post
    Getting a sample rate of 1us may require a dedicated micro just for data accumulation. I think 10us is feasible, and maybe faster but I don't know how fast. I'm sure it will depend on the clock speed of the micro and how much needs to be done in the processing loop. Probably just build it and see. I do think you want the ADC samples synched with the TX timing, even at 1us. That should be quite easy.
    Yes, the first phase of capture is made using DMA and feeding the FIFO, it is continous without any synch with the pulses.
    The second capture phase (made in parallel by the main program loop) is made by synchronizing the reading in the FIFO with the start of each period and accumulating the FIFO values into the slots of another array. The end result is an array made of as many slots as necessary to cover the whole pulse period. Example : period of 200µsec captured @ 1Msps generates 200 slots.
    Each slot is the integration of a number of consecutive periods (e.g. integration of 20 consecutive periods gives one net series of accumulated slots every 4msec).
    Next, the real windowing is defined by selecting the starting slot and width of each digital integration window and they are accumulated in as many virtual demodulators.
    Finally, the demodulators are used for the DSP and reporting.

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by moodz View Post

    What about MPLAB IDE ?? its free ..
    I was just listing the IDE's supporting ESP32.
    Visual Studio is also free.

    Leave a comment:


  • moodz
    replied
    Originally posted by Willy Bayot View Post
    Forgot to add one important IDE to the above list : Microsoft Visual Studio
    What about MPLAB IDE ?? its free ..

    Leave a comment:


  • Willy Bayot
    replied
    Forgot to add one important IDE to the above list : Microsoft Visual Studio

    Leave a comment:


  • Willy Bayot
    replied

    https://www.geotech1.com/forums/foru...676#post408676

    I catch the ball thrown by Dean Sarelius on the 'design challenge' forum

    I just submit this concept for discussions.

    I have studied in depth the most current architectures based on various types of ESP32 processors (including the double core ESP32-S3 @ 240Mhz).
    ​ This is a good comparison table between the various chip series : https://docs.espressif.com/projects/...omparison.html
    Look at the sum of advanced features given by the ESP32-S3

    This is becoming an entire new world with a lot of hardware and software support and a lot of CHEAP development platforms (Google with ESP32-S3, display images).

    The functional data processing modules of an AMX prototype could easily be assembled from a mix of those nice little modules.
    • Data capture module connected to a fast 24-bit ADC (parallel or SPI)
    • Main DSP module with data logging on SD-card
    • ready-made User interface :
    video : https://www.youtube.com/watch?v=j8THAc1sMww


    Video of simple VLF detector based on a single (old project, 4 years old) ESP32 module and developed under ARDUINO IDE​


    The main software development systems (free license) are:
    • The ESP-IDF from the ESPRESSIF chip producer
    • The ARDUINO IDE (yes, indeed!!)
    Technical ref manual : https://www.espressif.com/sites/defa...l_en.pdf#mcpwm
    ESP32-S3 datasheet : https://www.espressif.com/sites/defa...tasheet_en.pdf

    Leave a comment:


  • Teleno
    replied
    Originally posted by Carl View Post
    Addendum: You can fake integration by doing trapezoidal integration between points. But this does not average wideband noise the way a true integrator does.
    The ADS126X has a input low-pass filter that acts like an integrator. Page 37

    "The PGA programmable gain amplifier) input is equipped with a high frequency, electromagnetic-interference (EMI) input filter consisting of two 350-Ω input resistors, and several filter capacitors, as shown in the figure."

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by moodz View Post
    ...hmm if resolution is all you after then consider the ADS126X range of 32 bit ADCs from Texas instruments. They are $20 and theres people out there building uber precision voltmeters .. which is what 32 bits is good for.

    ..and theres a github project that interfaces the SPI interface to a raspberry pi. ..... more than enough grunt and cores to do the heavy lifting. ( python makes it easy peasy )


    https://github.com/AnnaKnapp/python_piadcs

    https://github.com/doceme/py-spidev
    moodz
    If we go the Direct Sampling track, we also need SPEED. I would say we would need a minimum of 1Msps (1µsec per sample)

    Leave a comment:


  • moodz
    replied
    ...hmm if resolution is all you after then consider the ADS126X range of 32 bit ADCs from Texas instruments. They are $20 and theres people out there building uber precision voltmeters .. which is what 32 bits is good for.

    ..and theres a github project that interfaces the SPI interface to a raspberry pi. ..... more than enough grunt and cores to do the heavy lifting. ( python makes it easy peasy )


    https://github.com/AnnaKnapp/python_piadcs

    https://github.com/doceme/py-spidev
    moodz

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by Carl View Post
    Getting a sample rate of 1us may require a dedicated micro just for data accumulation. I think 10us is feasible, and maybe faster but I don't know how fast. I'm sure it will depend on the clock speed of the micro and how much needs to be done in the processing loop. Probably just build it and see. I do think you want the ADC samples synched with the TX timing, even at 1us. That should be quite easy.
    1µsec sampling is easy under DMA if the ADC permits it.
    The capture of 0.7µsec slots into a cyclic buffer is something we have done practically using the procedure described in post #50.
    The sync with TX timing is made by the background loop reading the slots from the FIFO and processing them.

    Leave a comment:


  • Carl-NC
    replied
    Getting a sample rate of 1us may require a dedicated micro just for data accumulation. I think 10us is feasible, and maybe faster but I don't know how fast. I'm sure it will depend on the clock speed of the micro and how much needs to be done in the processing loop. Probably just build it and see. I do think you want the ADC samples synched with the TX timing, even at 1us. That should be quite easy.

    Leave a comment:


  • Willy Bayot
    replied
    I forgot to say in my previous post (#50) that a slot of the first half-period have to be SUBTRACTED from the corresponding slot of the second half-period before being accumulated into the virtual demods. The net effect is a doubling of the signal variation in that slot.

    Leave a comment:


  • Willy Bayot
    replied
    Originally posted by Carl View Post
    I continue to lean toward direct sampling. If you consider the TX waveform I proposed in post 25 and accept 2 samples per 25kHz pulse then the ADC must sample every 10us, or 100kHz. The micro would need to pull in 24 bits of serial data every 10us. Many of the better micros have SPI that runs at 25-50MHz. Let's assume 25MHz; pulling in 24 bits will take slightly more than 1us. So sampling at 10us looks fairly easy.

    Inside the micro we have data coming in every 1us. But a typical processing loop runs every 5ms or so, therefore 1us is way too fast. So you simply DMA the data to a fast array accumulator that bins the data you want to keep. Each complete TX cycle (1x5kHz + 5x25kHz) takes 400us, so if we make the processing loop 4ms then that is an even 10 TX cycles, or 400 ADC samples. So every 4ms you transfer the array data into the processing loop and work away. Or 6ms for an even 15 TX cycles, or 600 samples.

    A key to making this work is to automate and autonomize everything possible. This means autonomous clocking (both TX & ADC), ADC DMA with an interrupt-triggered fast accumulator, and an RTOS-controlled processing loop.

    I am not opposed to using an FPGA but HDL that is not one of my skills. Many years ago at White's I took a day-long hands-on FPGA lab but I don't remember any of it. I really think a good micro (and just one) can do the whole thing.
    Without going into real implementation at this point of the discussion, from the latest posts, could we then conclude that we go together to discuss the details of the DIRECT SAMPLING track?
    Further on, I also personally think that going to FPGA in this project would be an overkill and a useless complexity in the development cycle.

    The capture process I favour is the following:
    • Continuous DMA-based ADC data capture into a large cyclic buffer (FIFO) with a capture rate of minimum 1Msps. Each slot is 1µsec wide. No synchronization with the pulse timing.
    • The capture loop is synchronized with the pulse timing, it makes a cherry picking to select specific slots in the FIFO and accumulates them into the correct virtual demodulator.
    • In order to simulate the analog integration windows, several consecutive slots can be added together (integrated) into the same virtual demodulator. e.g. 10 consecutive slots accumulated into the same10µsec wide demod
    • The capture loop is executed as many times as necessary over consecutive signal half-periods( i.e. signal decays) to get a good integration over time in all the defined demodulators.
    • Every say, 4msec, ( 40 loops for a half-period of 100µsec) , the loop is terminated and the DSP starts working on the current demodulator values after which the demodulators are cleared.
    • During this process, the ADC capture continues without interruption into the FIFO. Thus, nothing is lost except a few pulse periods duribg the reporting duration which can be longer.
    If we use a AD7760, we could get slots of 0.4µsec under DMA, thus, a 10µsec virtual window can accumulate 40 consecutive slots instre

    Leave a comment:


  • Carl-NC
    replied
    Originally posted by Altra View Post
    Thanks, my question was not worded correctly. I didn't mean to imply using the adc as an integrator directly. It was more about controlling the sample start points and bins.
    Yes, you can very accurately control the start points. Not sure what you mean by bins, but binning the data is software dependent. The way I would do it is to set up the ADC with a fixed sample clock (say, 10us) offset from the TX edges exactly where I want it. Then use the ADC data-ready (DR) pulse to trigger an interrupt which DMAs the data and calls a fast binning routine. When a binning set is done (say, every 16 TX cycles) the binning routine queues the data to an RTOS task.

    Leave a comment:

Working...
X