AMX Digital

[Carl-NC]

Carl, using direct sampling can the adc be controlled to sample precisely at the traditional points in time and duration? Like a sampling integrator?

No, you can control when it samples but you do not get any time integration. From post 3:

It should be noted that analog demods have the advantage of doing real-time integration, whereby you are integrating the RX signal as long as the demod switch is closed. This helps with SNR and also with implementing GB. Direct sampling cannot do this, you get an instantaneous point and that's all (think about this for GB).

Addendum: You can fake integration by doing trapezoidal integration between points. But this does not average wideband noise the way a true integrator does.

[Altra]

Thanks, my question was not worded correctly. I didn't mean to imply using the adc as an integrator directly. It was more about controlling the sample start points and bins.

[Carl-NC]

That is just the way I did code on a PIC32MX to direct sample a PI.
The PIC hardware did all timing from TX pulse to ADC sampling with DMA.

Well there ya go, I think we have a new project leader! This reminds me, I should expand on the previous question. An analog integrator integrates both during its "on" time and also during successive samples. Using direct sampling, you can still "integrate" (or average) over successive samples and beat the noise down that way. Every time you double the average you get a 3dB processing gain. So in my previous example if we average 16 TX cycles (for a processing loop speed of 6.4ms) we would see a 12dB SNR improvement, which looks like 2 extra ADC bits.

[Carl-NC]

Thanks, my question was not worded correctly. I didn't mean to imply using the adc as an integrator directly. It was more about controlling the sample start points and bins.

Yes, you can very accurately control the start points. Not sure what you mean by bins, but binning the data is software dependent. The way I would do it is to set up the ADC with a fixed sample clock (say, 10us) offset from the TX edges exactly where I want it. Then use the ADC data-ready (DR) pulse to trigger an interrupt which DMAs the data and calls a fast binning routine. When a binning set is done (say, every 16 TX cycles) the binning routine queues the data to an RTOS task.

[Willy Bayot]

I continue to lean toward direct sampling. If you consider the TX waveform I proposed in post 25 and accept 2 samples per 25kHz pulse then the ADC must sample every 10us, or 100kHz. The micro would need to pull in 24 bits of serial data every 10us. Many of the better micros have SPI that runs at 25-50MHz. Let's assume 25MHz; pulling in 24 bits will take slightly more than 1us. So sampling at 10us looks fairly easy.

Inside the micro we have data coming in every 1us. But a typical processing loop runs every 5ms or so, therefore 1us is way too fast. So you simply DMA the data to a fast array accumulator that bins the data you want to keep. Each complete TX cycle (1x5kHz + 5x25kHz) takes 400us, so if we make the processing loop 4ms then that is an even 10 TX cycles, or 400 ADC samples. So every 4ms you transfer the array data into the processing loop and work away. Or 6ms for an even 15 TX cycles, or 600 samples.

A key to making this work is to automate and autonomize everything possible. This means autonomous clocking (both TX & ADC), ADC DMA with an interrupt-triggered fast accumulator, and an RTOS-controlled processing loop.

I am not opposed to using an FPGA but HDL that is not one of my skills. Many years ago at White's I took a day-long hands-on FPGA lab but I don't remember any of it. I really think a good micro (and just one) can do the whole thing.

Without going into real implementation at this point of the discussion, from the latest posts, could we then conclude that we go together to discuss the details of the DIRECT SAMPLING track?
Further on, I also personally think that going to FPGA in this project would be an overkill and a useless complexity in the development cycle.

The capture process I favour is the following:

• Continuous DMA-based ADC data capture into a large cyclic buffer (FIFO) with a capture rate of minimum 1Msps. Each slot is 1µsec wide. No synchronization with the pulse timing.
• The capture loop is synchronized with the pulse timing, it makes a cherry picking to select specific slots in the FIFO and accumulates them into the correct virtual demodulator.
• In order to simulate the analog integration windows, several consecutive slots can be added together (integrated) into the same virtual demodulator. e.g. 10 consecutive slots accumulated into the same10µsec wide demod
• The capture loop is executed as many times as necessary over consecutive signal half-periods( i.e. signal decays) to get a good integration over time in all the defined demodulators.
• Every say, 4msec, ( 40 loops for a half-period of 100µsec) , the loop is terminated and the DSP starts working on the current demodulator values after which the demodulators are cleared.
• During this process, the ADC capture continues without interruption into the FIFO. Thus, nothing is lost except a few pulse periods duribg the reporting duration which can be longer.

If we use a AD7760, we could get slots of 0.4µsec under DMA, thus, a 10µsec virtual window can accumulate 40 consecutive slots instre

[Willy Bayot]

I forgot to say in my previous post (#50) that a slot of the first half-period have to be SUBTRACTED from the corresponding slot of the second half-period before being accumulated into the virtual demods. The net effect is a doubling of the signal variation in that slot.

[Carl-NC]

Getting a sample rate of 1us may require a dedicated micro just for data accumulation. I think 10us is feasible, and maybe faster but I don't know how fast. I'm sure it will depend on the clock speed of the micro and how much needs to be done in the processing loop. Probably just build it and see. I do think you want the ADC samples synched with the TX timing, even at 1us. That should be quite easy.

[Willy Bayot]

Getting a sample rate of 1us may require a dedicated micro just for data accumulation. I think 10us is feasible, and maybe faster but I don't know how fast. I'm sure it will depend on the clock speed of the micro and how much needs to be done in the processing loop. Probably just build it and see. I do think you want the ADC samples synched with the TX timing, even at 1us. That should be quite easy.

1µsec sampling is easy under DMA if the ADC permits it.
The capture of 0.7µsec slots into a cyclic buffer is something we have done practically using the procedure described in post #50.
The sync with TX timing is made by the background loop reading the slots from the FIFO and processing them.

[moodz]

...hmm if resolution is all you after then consider the ADS126X range of 32 bit ADCs from Texas instruments. They are $20 and theres people out there building uber precision voltmeters .. which is what 32 bits is good for.

..and theres a github project that interfaces the SPI interface to a raspberry pi. ..... more than enough grunt and cores to do the heavy lifting. ( python makes it easy peasy )


https://github.com/AnnaKnapp/python_piadcs

https://github.com/doceme/py-spidev
moodz

[Willy Bayot]

...hmm if resolution is all you after then consider the ADS126X range of 32 bit ADCs from Texas instruments. They are $20 and theres people out there building uber precision voltmeters .. which is what 32 bits is good for.

..and theres a github project that interfaces the SPI interface to a raspberry pi. ..... more than enough grunt and cores to do the heavy lifting. ( python makes it easy peasy )


https://github.com/AnnaKnapp/python_piadcs

https://github.com/doceme/py-spidev
moodz

If we go the Direct Sampling track, we also need SPEED. I would say we would need a minimum of 1Msps (1µsec per sample)

[Teleno]

Addendum: You can fake integration by doing trapezoidal integration between points. But this does not average wideband noise the way a true integrator does.

The ADS126X has a input low-pass filter that acts like an integrator. Page 37

"The PGA programmable gain amplifier) input is equipped with a high frequency, electromagnetic-interference (EMI) input filter consisting of two 350-Ω input resistors, and several filter capacitors, as shown in the figure."

[Willy Bayot]

https://www.geotech1.com/forums/foru...676#post408676

I catch the ball thrown by Dean Sarelius on the 'design challenge' forum

I just submit this concept for discussions.

I have studied in depth the most current architectures based on various types of ESP32 processors (including the double core ESP32-S3 @ 240Mhz).
This is a good comparison table between the various chip series : https://docs.espressif.com/projects/...omparison.html
Look at the sum of advanced features given by the ESP32-S3

This is becoming an entire new world with a lot of hardware and software support and a lot of CHEAP development platforms (Google with ESP32-S3, display images).

The functional data processing modules of an AMX prototype could easily be assembled from a mix of those nice little modules.

• Data capture module connected to a fast 24-bit ADC (parallel or SPI)
• Main DSP module with data logging on SD-card
• ready-made User interface :

video : https://www.youtube.com/watch?v=j8THAc1sMww


Video of simple VLF detector based on a single (old project, 4 years old) ESP32 module and developed under ARDUINO IDE


The main software development systems (free license) are:

• The ESP-IDF from the ESPRESSIF chip producer
• The ARDUINO IDE (yes, indeed!!)

Technical ref manual : https://www.espressif.com/sites/defa...l_en.pdf#mcpwm
ESP32-S3 datasheet : https://www.espressif.com/sites/defa...tasheet_en.pdf

[Willy Bayot]

Forgot to add one important IDE to the above list : Microsoft Visual Studio

[moodz]

Forgot to add one important IDE to the above list : Microsoft Visual Studio

What about MPLAB IDE ?? its free ..

[Willy Bayot]

What about MPLAB IDE ?? its free ..

I was just listing the IDE's supporting ESP32.
Visual Studio is also free.