uPC Controlled PI

[Carl-NC]

I was trying to think of a name that includes "King"... how about the KingFisher PI ? King Cobra is also good, but is a current Kellyco model.

[joecoin]

Thank you for the vote of confidence!

Yes, I would like to see it completed and be a positive contribution to the 'community'.

Ah, a name. I am completely at a a loss! Any suggestions? I am not afflicted with NIH syndrome.

Regards,
J. L. King

Since you're using a ISO7220M, cal it an ISO(In Search Of).?

[KingJL]

Eagle Files for uPC controlled PI

The Eagle files for the current state of the design are in the zip attachment. It was developed in Eagle version 5.3.0

I had a board layout with routing completed but I tore it up. (1) I was not happy with the layout; (2) I had removed one of the ISO7220M's; (3) I changed the package of the UC3710 from a DIP8 to a 5 pin T220. I am going to attemp again the layout. This area is not my strong suit. If anyone out there has a knack for this, please assist.

My intent is to get a prototype of the TX and RX frontend done with 2 sided thru hole technology (except for the ISO7220M which is only available in surface mount). I plan on using the laser printer method to create a prototype board. After the prototype is tested and proven, I would like to have the design done in SMT (IC's SOIC, passives 805).

Regards,
J. L. King

[KingJL]

JL,

You have a good design proposal, not far from what I was working toward with HH3.

Thank you for the vote of confidence!

Is this something you want to follow through to a completed design?

Yes, I would like to see it completed and be a positive contribution to the 'community'.

Give it a name and I'll move it to the "Projects" area where it'll get more exposure and participation.

Ah, a name. I am completely at a a loss! Any suggestions? I am not afflicted with NIH syndrome.

Regards,
J. L. King

[Carl-NC]

JL,

You have a good design proposal, not far from what I was working toward with HH3. Is this something you want to follow through to a completed design? Give it a name and I'll move it to the "Projects" area where it'll get more exposure and participation.

- Carl

[KingJL]

Interrupt Service Routine Update

Fixed an over-sight that I found while testing the interrupt handler. In the previous version the sample_address was simply incremented at the trailing edge of the sample pulse. Exploring all of the options available, there existed the posibility that the configuration would not use 8 samples. When this condition occurs the sample address would not be in sync every TX cycle. Modified the code to re-initialize the sample address to 0 as part of the TX start service. This addition added 4 machine cycles (0.333 usec) to the TX service routine.

Regards,
J. L. King

[KingJL]

Updated Documentation

I have updated the design document to the current hardware/software implementation.

Regards,
J. L. King

[KingJL]

LPF spec revision

I am switching the IC's that will be used for the LPF's. Instead of the MAX260's, I am going to use TLC14's (TI). ~1/10th the current drain, easier uPC interface, sharper co (4 pole vs 2 pole). Downside, I have to use twice as many. But, still much less current drain and ~same overall footprint!

Regards,
J. L. King

[KingJL]

I have been working on this design for a while now. I had intended that it be a collaborative effort with the CDG. But since the CDG has been in effect dissolved, I am going to post the current effort here until I find a more appropriate forum subject.

Originally, this was intended to be predominately digital processing of the sampled RX signal. But implementing this was beyond the practical capabilities of the available processors. Even an 80MHz PIC32 was borderline for the DSP that had to be accomplished and still leave enough processor reserve to handle the user interface and user feedback that would be needed.

So, the design was reworked to provide analog conditioning of the RX data and the make it available to the uPC for discrimination and deterministic processing. For signal conditioning uPC control is stressed vs. uPC signal processing. The intended design makes use of digital control of RX gain, LP filter control, as well as the documented PI timing.

The design is intended to provide a robust and flexible base with which to offer many options for PI MD operation. It is also intended to make use of Carl's USB P18F4550 board for operation and control.

The current design intention is for it to be made up of 2 boards. One board to be the PS, TX, and RX. The second board would be the 8 channel S&H, ADC, and audio.

I have completed the design of the PS/TX/RX board (Eagle) and am in the process of building the prototype. I have coded the PIC code to generate the TX/RX timing signals. I am currently waiting for an 18F4550 to verify and test the PIC code that is designed to date. I have checked it out using a 18F4431 @ 20MHz (which is to slow to achieve timing requirements) that I have, but I need to verify timing and operation at 48MHz.

The attached zip file contains the document that I have created (to help keep my project somewhat focused), and the PIC code to date.

Comments are welcomed.

Regards,
J. L. King