uPC Controlled PI

[Monolith]

Kingfisher project

Are there any updates on the Kingfisher project?

Monolith

[KingJL]

I have solved the issue. Changed blocking methodoly slightly. Use the FQN1N60C as in the previous schematics, changed the VP3203 so that during the block period it shunts the signal to ground. It uses the same gate signal as the FQN1N60C. Minimal switch noise (20ns 200mv spike 10ns after unblock as seen at the output of the pre-amp). This small spike is blocked from the AD600 by the AD600 gate. Can sample at 5us after TX with no problem.

Will take pics of o'scope test points after i clean the board up a bit. A schematic of the changes is included here. I kludged the board to test it and it works. No need for different MOSFETS. Now to clean it up a bit.

[bugwhiskers]

If you click on the following link and go to the bottom of the thread then scroll up until you see some schematics. Sheet 2 of 4 shows a very elegant 1 chip solution to drive the P & N channel Fets as well as the MOSFET driver chip with the correct voltages for each.

http://goldprospecting.invisionplus....t=0&#entry4419

regards
bugwhiskers

[bugwhiskers]

Hi KingJL,

Considering the series diode in the TX coil circuit to minimise the effect of MOSFET capacitance and the front end blocking FET's in ML PI detectors to speed things up one must ask then why do they sample so late. The SD2000 timing diagrams show a whopping 45 uS sample delay after the 240uS TX pulse. I tried the blocking FETs but the ringing caused the earliest sample time to blow out past the ordinary current limiting resistor and clipping diodes arrangement.

I think the answer lies in the GB. In a late sample the ratio of ground to target will be much greater. If you don't plan to use any form of GB then the standard approach will probably work much better.

regards
bugwhiskers

[KingJL]

I have changed the schematic and am modifying my board to facilitate the changes.

Although the changes provide a more usable front end, the VP3203 is still the wrong MOSFET to use here (too much input capacitance). I am trying to obtain some samples of the Zetex ZVP2106, which should be much better. That seems to be about the best that I can locate with a TO92 package. The best I have found overall is the Fairchild VP304 and the Philips BSS84, but these are only available in SMD packages.

[KingJL]

Well, I think I have designed a fix for the Rx blocking circuitry that works superbly (simulated). Next step is to implement and test in the real world. The simulation suggests that changing the resistor in the collector of the 2N5088 to 220 ohms gives much faster turn-off. Putting an 820 ohm in the base circuit limits the 2N5088 cuurent to 90ma peak during the block pulse. The gnd connection of the TPS2814 is changed from -12V to -5V. This solves the overdrive of the MOSFETS. A 4148 diode between the collector of the 2N5088 and -5V prevents negative overdrive of the TPS2814 inputs. The 2N4403 is added to derive a AD600 Rx gate signal that is "stretched" to 0.7 usec after MOSFET turn-off. I also am removing the reversed parallel diodes after the P-MOSFET (at the input to the AD797). Also changing the resistor between AD797 input and ground to a 8K2.

I believe I can make the above changes with the exixting board (though somewhat hacked up) to enable further testing.

Attached is the schematic that I captured from the LTSPICE simulations of the changes. The LTC1693 is substituted for the TPS2814 in the model.

[KingJL]

... RX blocking appears to be now working. I believe I have to find another P-channel MOSFET for the RX block. There appears to be too much capacitive coupling of the gate signal to the output. I get about a 100mv leading and trailing edge spike. I will research this to see if there is a better component for this.

Well I'm slowly getting back on project. Still no pictures or further check out. Have been focusing on the blocking MOSFETs and the switching spike. I think I have identified the main problem. The current design has the gate voltage to the MOSFETs switching between +5v & -5v. This is driving the gates 5v past the switch-off voltage. The PMOS should have the gate voltage switching between 0 & -5v; The NMOS should have the gate voltage switching between 0 & +5v. Verified the problem with simulation models. With the gates switching between -5v & +5v, simulation runs exhibit the same charactaristic as observed in the actual circuit. Changing the gate switching voltages as described above decreased the switching noise spike considerably. Now to change the actual circuit!! Need to study this for a while to find the best way without having to re-make the board until the rest of testing is done.

Regards,
J. L. King

[KingJL]

Got sidetracked this week. Had to get the camper ready for a trip to the NC coast (Carolina Beach) for Xmas. Will return to the project after I return on the 1rst.
Everyone have a great holiday season.
Regards,
J. L. King

[KingJL]

Checked out the AD797 pre-amp. Only problem was a 17mv output offset. With the offset balance as designed in the schematic, could not completely balance. The offset would vary 17mv-37mv. Ripped out the offset balace and replaced with a traditional offset balance adjustment circuit consisting of a 100K multi-turn trimmer between +5V & -5V, fed through a 2200 ohm to pin2 of the AD797. Ahhhh, that is better!

Next in line is to set up a gain conrol input and test out the AD600. So far, so good!

The AD797 offset balance citcuit changes will be included in the next version of the schematic and PCB.

After I complete testing of the AD797, I will hook up a coil and take some oscilloscope pictures of the signals at different test points and post them in this forum.


Regards,
J. L. King

[KingJL]

Well, fired up the beast! At first, no voltages except for 12V. Lost a ground somewhere! Found the lost ground; topside connection of U302 pin6. Repaired that and now we have all voltages present. Measured quiesent voltages for all TX components. The output of the ISO7220M looks questionable.

Apply ground to the two input pins that go to the ISO7220M. Everything in the TX looks acceptable. Now to hook up the uPC and check out TX. Signal looks great. The ISO7220M does a great job of shifting the level to work with the negative voltage TX.

Now to check out RX blocking circuit. The inut to the TPS2814 pins 2&3 appears to be wrong! The signal is a neagtive going signal (OK so far) going from -1.2V to -12V (should be 5V to -12v). Also notice that the 2N3904 is stretching the PW of the blocking signal by ~2.5usec. I find that the Eagle libraries package for the 2N3904 have the pins reversed. I fix the package and also change the transistor to a 2N5088. Now the blocking signal to the TPS2814 goes from 5V to -12V. Outputs to from the TPS2814 to the MOSFET gates are correct. The 2N5088 only stretches the signal by .5 usec. The 3904 is too slow for use in a high speed switch circuit.

Something in the blocking circuit is not functioning properly as I have a +5V with negative going (-12V) signal at the drain of Q301. Well, I have the orientation of BOTH MOSFETS in the RX blocking circuit reversed. Reverse the 2 MOSFETS and retest. RX blocking appears to be now working. I believe I have to find another P-channel MOSFET for the RX block. There appears to be too much capacitive coupling of the gate signal to the output. I get about a 100mv leading and trailing edge spike. I will research this to see if there is a better component for this.

The timing circuitry for both the TX and RX seem to be working as intended (except for the feedthru of th RX block gate signal). This checks out the digital section and the uPC interface.

Next is to check the analog portion (RX front-end).

Attached is the updated eagle files and the board layout bmp files that include all corrections to date.

Regards,
J. L. King

[KingJL]

Populated Board

Well, all components are mounted on the board. I painstakingly checked continuity between all components as I progressed. As all of you who have done this know, two sided boards without plated thru-holes make it especially important to insure electrical connection on both top and bottom of component mounting holes.

Now on to testing everything!

[Carl-NC]

Went back to Circuits I (literally!) and reviewed the math on critical damping. The equation for the curve is

v(t) = Io/C*t*e(-t/2RC)

where Io is the coil current at t=0+ turn-off.

If you take the derivative the the peak occurs at

dv/dt = 0 @ t=2RC

and the peak voltage is

v(2RC) = 2*Io*R*e(-1) = 0.734*Io*R

For your case, Io = 600v/(0.734*760) = 1.075A.

- Carl

[Carl-NC]

Eh, on the way in to work I realized that (duh) I neglected the entire mathematical response for the RLC circuit. Even with an ideal switch the peak response is not instantaneous, but occurs a little later in time and at a lower value than I*Rd. It's been many many years since I've done the math on this, so I need to review it.

- Carl

[Carl-NC]

Yes, you're right, the peak voltage is not instantaneous because the MOSFET has a linear turn-off instead of abrupt. This allows some bleed-off before the switch is fully open. It's dependent on the quality of the gate driver; put a variable series resistor in the gate and watch what happens. Furthermore, a 600V MOSFET probably clips at ~650V so you can push things a little harder. So, 1.2 amps is probably fair.

- Carl

[KingJL]

Initial peak voltage is I*Rd, so you need a max I = 600/760 = 800mA.

I understand that for pure LR. But on my working HH, I was seeing ~1.1-1.2 amp to get a 600V flyback spike (w/680 Rd). I think that the reason is the circuit capacitance and the leading edge voltage does not get fully developed accros Rd.