Preamp

[Teleno]

What changes with temperature? If you put an ntc in parallel with R16 won't it heat up and change value a lot? Maybe it could be part of voltage divider for the gate drive. The MCU drive is also a good idea , particularly it is can have an auto adjust , or maybe auto cal function.

The MOSFET current decreases with temperature (Rds_on increases), so an NTC would reduce the source resistance by the same ratio (hopefully), achieving temperature independency.

Auto cal. is another option, but not exclusive, since both methods can be implemented. Calibration would adjust to different coils and Tx currents.

[Teleno]

Be careful, could be already patented by ML.

Sure, as of now the circuit is available in the public domain and indexed by Google: http://elcid.demon.nl/metal_detector/

That should stop them.

[Old cart]

Dual coil and temp compensation

Perhaps, but let's keep it simple by now and prove the concept on a monocoil first. If it works, then we can move further.

Coming back to the active damping ... the current sink circuit is very simple:



but it's very dependent on temperature, any ideas on how to compensate it? I was thinking an NTC in parallel with R16 but perhaps there are better ways.

Otherwise it will be left as another task for the MCU (one more DAC output).

I for one like the idea of a dual coil. That being said I have never used on a PI machine so don't know how they perform.

What changes with temperature? If you put an ntc in parallel with R16 won't it heat up and change value a lot? Maybe it could be part of voltage divider for the gate drive. The MCU drive is also a good idea , particularly it is can have an auto adjust , or maybe auto cal function.

[WM6]

Be careful, could be already patented by ML.

[Qiaozhi]

But WHAT IF you use a dual coil setup? Optimize for a PRF of say 1200Hz? Would that not be the basis of a fantastic nugget hunter?

Or you could follow the example of the improvised coil thread and go for a triple coil setup.

[Teleno]

But WHAT IF you use a dual coil setup? Optimize for a PRF of say 1200Hz? Would that not be the basis of a fantastic nugget hunter?

Perhaps, but let's keep it simple by now and prove the concept on a monocoil first. If it works, then we can move further.

Coming back to the active damping ... the current sink circuit is very simple:



but it's very dependent on temperature, any ideas on how to compensate it? I was thinking an NTC in parallel with R16 but perhaps there are better ways.

Otherwise it will be left as another task for the MCU (one more DAC output).

[Sean_Goddard]

But WHAT IF you use a dual coil setup? Optimize for a PRF of say 1200Hz? Would that not be the basis of a fantastic nugget hunter?

[Teleno]

This version includes a floating current sink (R16/U3) based on a high voltage depletion mosfet DN3545 or similar.

Source resistance R1 is fixed at 500 Ohm. Damping is active (see Moodz) by varying R16 depending on Tx current and coil.

Advantages:

- Less noise than the previous design (lower R1) and largely independent of the coil.
- Higher gain (ratio R2/R1 is larger).

Disadvantages:

- R16 depends on the L/C of coil and on the Tx current. Adjustment is delicate and sensitive to temperature.
- There's a small delay penalty for faster coils (around 1us)

[Teleno]

If you think about it a bit further, the effects you mention, while completely valid, are of the 2nd order. Your useful signal is falling well under 100Hz. All the interferences above 100Hz will cancel out. Some even improve dithering.

The interference from the Tx pulse is repetitive with the same period as the signal. Not useful for dithering.

Anyway my design is open to everybody, modify according to personal preference and please, do share.

[Davor]

If you think about it a bit further, the effects you mention, while completely valid, are of the 2nd order. Your useful signal is falling well under 100Hz. All the interferences above 100Hz will cancel out. Some even improve dithering.

[Teleno]

I beg to differ in the part of PSRR influence on EF. Few people understand what EF actually does, but in case you are worried about influence of PSRR on signal sampling arithmetics, you should try the voltage reference trick I mentioned above.

The ADC voltage reference input effectively works as a 1 quadrant divider. It thus normalises binary data.
Say, Vcc rises for 10%, the ADC step is raised also by 10%. If a signal is also risen by 10% due to a Vcc jump, it will be presented with a same binary value after ADC.

It sounds like a good trick based on the assumption (generally valid) that the power supply and the signals vary in the same percentage.

This may not be the case in these situations:

1. During ADC conversion time (65us in an ATtiny), the signal is held constant in the sampling capacitor but the reference is changing with the power supply.

2. Non-linearities in amplifier stages cause the percentage in the signal to deviate from the power supply's.

My amplifier is an atttempt a pushing the specs to the limit (fast, low noise) so I'm not taking shortcuts that would be perfectly acceptable in other projects.

[Davor]

I beg to differ in the part of PSRR influence on EF. Few people understand what EF actually does, but in case you are worried about influence of PSRR on signal sampling arithmetics, you should try the voltage reference trick I mentioned above.

The ADC voltage reference input effectively works as a 1 quadrant divider. It thus normalises binary data.
Say, Vcc rises for 10%, the ADC step is raised also by 10%. If a signal is also risen by 10% due to a Vcc jump, it will be presented with a same binary value after ADC.

[Teleno]

Well, I was not much around here lately, so I couldn't interfere before. I fail to see any DC referencing mechanism. Are you going to set the DC bias by means of adjusting the source resistances for the given FETs, or am I missing the point?

If you look at the top-right corner of the schematic you can see the instructions (in blue) to set the DC working points. They're set by adjusting the source resistances of the JFETS.

1. Adjust R3 to obtain 6V at point "Vtest".
2. Then adjust R5 to obtain the desired baseline at "Vout", something between 200 mV - 500 mV is fine.

U2 can be any fast JFET OpAmp. Rail-to-rail variants are not necessary because the inputs will vary around the mid-point of the power supply (6v) and MOSFET M2 provides the rail-to-rail output by subtracting its own threshold from the OpAmp's output.

Same goes with PSRR obsession. Since you use ADC further on, and you use the very same power supply in a whole design, wouldn't it be more efficient to simply use voltage divider from the PSU as a voltage reference for ADC? High frequency components will only act as a kind of dithering anyway.

Is PSRR is poor, the power supply recovery ramp (that follows the high current Tx pulses) will add different levels to the EF component at the signal sampling point and at the EF sampling point. What's worse, the power component will vary as the battery discharges. This is not good if you want to do Earth Field and Ground Balance. To avoid this I make sure the PSRR is enough to push power fluctuations below the output noise at the very least.

I prefer a good PSRR as it makes the signal a lot more solid. Besides, it's easy to achieve.

The ADC works on a regulated 5V supply. I might look at using this supply (which already has a good PSRR) for biasing instead of the JFETs, but I'm afraid the schematic won't get any simpler than this and then there's the high noise noise of the regulator, a problem the JFETs don't have.

[Davor]

Well, I was not much around here lately, so I couldn't interfere before. I fail to see any DC referencing mechanism. Are you going to set the DC bias by means of adjusting the source resistances for the given FETs, or am I missing the point?

It is not critical since EF sample is applied further on, so DC reference may float. But some general range must be set.

Same goes with PSRR obsession. Since you use ADC further on, and you use the very same power supply in a whole design, wouldn't it be more efficient to simply use voltage divider from the PSU as a voltage reference for ADC? High frequency components will only act as a kind of dithering anyway.

[Teleno]

Be careful when touching the ramp, since the wanted signal is riding atop that ramp

That's why I use the ramp as the reference, to separate the signal from the ramp.

The base of Q2 is referenced to the ramp, J2 with its gate attached directly to the ramp provides a steady collector voltage (rerefenced to the ramp) for Q2. Actually the 1st stage suppresses the ramp by -80 dB (at Vtest) and outputs a signal referenced to GND via a high output impedance cascode Q2/J2.

The second amplifier stage is referenced to GND. The MCU and its ADC are also referenced to GND. The offset bias for the OpAmp is isolated from the ramp by the current source J3/J4 which provides -80 dB suppression.

I believe everything has been though out and the amplifier is ready for breadboarding. Is anyone up to designing the PCB?