Preamp

[ODM]

Sorry, didn't state myself clearly; by cold end I mean the end where voltage swings are pretty small compared to the hot end that swings from battery voltage to flyback peak.

Be careful when touching the ramp, since the wanted signal is riding atop that ramp Most differential frontends use the coil cold end directly as a reference, which rids the signal of any capacitor charge ramp issues - until the reference changes, anyway. These reference changes are always a chance for some surprise pains, thus it's a good idea to reference one's A/D conversion to the same supply as the coil driver is. Microcontroller single ended ADCs can be nasty about it and their supply rejection generally goes down the drain when coupling their reference anywhere except the mcu's ground.

[Teleno]

The only caveat I see on a quick glance is that there's no reference from the coil's cold end (VDD) after the first amp stage. Usually translating a signal from a reference to another is done by an instrumentation amplifier kind of circuit that takes a signal and a reference, and translates it to another signal with a separate reference.

The cold end is referenced via R1 and R6 to the "virtual ground" of Q2's emitter. This is a common base configuration with gain aaprox. R2/R1.

This is just a gut feeling but I imagine your PSRR stems mostly from having amplifiers referenced via current source and resistor combinations to both ends of the battery without a common signal ground.

Certainly there's no common signal ground, but the PSRR is necessary whenever a fixed reference is required expecially if that reference is going to be amplified. Although C2 attenuates the supply swings coused by the Tx pulses, the slow recovery means the cap is still charging while the signal is being sampled. This supply ramp needs to be eliminated fro the output.

[ODM]

Looks nice with a reasonable number of parts for a discrete frontend. When you prototype this one I recommend building it on plain copper board. How fast is your 'scope, analog/digital?

The only caveat I see on a quick glance is that there's no reference from the coil's cold end (VDD) after the first amp stage. Usually translating a signal from a reference to another is done by an instrumentation amplifier kind of circuit that takes a signal and a reference, and translates it to another signal with a separate reference.

This is just a gut feeling but I imagine your PSRR stems mostly from having amplifiers referenced via current source and resistor combinations to both ends of the battery without a common signal ground.

[Teleno]

This version uses improved current sources for better PSRR at the two biasing nodes (Q2/D3 and R11/R12).

The output can swing between 270mV and 5V.
Gain: 480
PSRR: -64 dB
Sampling delay: 6 usec.
Input referred noise level: 2.5 uV
Output noise level: 1 mV



Power Supply Rejection Ratio:

[ODM]

Reading the documentation on their opamp simulation models is a good starting point. In the earlier case I presented, the opamp's own PSRR that would be around 40-80dB would largely be swamped by the circuit's own supply rejection ratio that was up to 60-100dB worse (yes, that means supply variations actually show up in output with gain instead of attenuation).

It's important to do these simulations as straight up AC simulations, injecting the stimulation individually to each path (ac voltage in series with path) to see what individual paths have the largest effect on the overall output. Don't use a noise simulation for measuring response for individual distubance sources. Noise simulation is useful but it is very easy to interpret wrong.

To simulate an opamp's PSRR you need the complete simulation model for that opamp, some manufacturers do supply their simulation models which is nice. It's easy to check whether they match the presented PSRR spec with the AC simulation's AC voltage injected into the supply. If the simulation model does not have PSRR support it is hardly LTSpice's fault, luckily adding simulation parameter listings is easy

[Davor]

The most Spice models simplify opamps by means of modelling only the input circuitry, and the rest is just a piecewise linear "gain block". In most cases it is OK, as such models run much faster than the full model with all transistors accounted for. Bur as you say, there are cases it is not good enough.

[Teleno]

Bad news, OpAmp (LT)Spice models are generally not suitable for PSRR simulations (Power Supply Rejection Ratio). The results and the characteristics in the datasheets do not match by a large margin. Actually LTPsice grossly underestimates the PSRR.

[Old cart]

The answer is no, the LM337/LM317 are not fast enough and slow the samoling down by 4usec.

The current sources/sinks have to be fast, so RF JFETs are the only option.

Did you answer your own question?

[Teleno]

I think current sourced/sinks J1/R13 ahd J2/R14 should be replaced by shunt bandgap references (LM337/LM317) to achieve maximum ripple rejection. Other ideas?

The answer is no, the LM337/LM317 are not fast enough and slow the samoling down by 4usec.

The current sources/sinks have to be fast, so RF JFETs are the only option.

[Teleno]

I think current sourced/sinks J1/R13 ahd J2/R14 should be replaced by shunt bandgap references (LM337/LM317) to achieve maximum ripple rejection. Other ideas?

[Teleno]

It's a novel design, but for the following effects I can't agree that this amplifier will behave indepently of noise riding on battery voltage.
* The ADC is tied to a fixed reference based on the logic voltage ground.
* Supply noise on the negative rail will affect the constant current drives.
* The JFET input amplifier is referenced to -Vbatt*(5/7), and this is multiplied by a gain of feedback resistor and equivalent of voltage divider, which means the PSRR is -24dB! I suggest coupling this stage with a decent capacitor to the reference of the previous stage, preferably no ceramics or failing that a good quality NP0 since it's a signal carrying cap.

Thanks for your input, good to meet someone who understands circuit design.

You're right, the digital ground and the OpAmp input are not referenced to -Vbatt while the signal at R2 is.

To remedy these issues the voltage divider is scrapped and I'm using a current source on R11. This the Thevenin equivalent of a steady voltage source in series with R11. It determines the baseline of the output vout.

The digital ground referenced to +Vbatt is also scrapped, this new version uses -Vbatt as the common ground to all circuits.

The role of the JFET OpAmp in the new design is no longer to provide a gain block, but buffering (gain close to 1) and voltage-to-current conversion. This lowers the speed requirements for the OpAmp since extremely high slew rates are no longer necessary. Common ICs such as TL071 or LF357 can be used with little or no speed penalty compared to AD8610.

Gain is achieved by a current mirror at the OpAmp output which also provides referencing to -Vbatt to isolate the output from power ripples.





AC analysis of a reference signal Vn1 riding on battery voltage:






The premp stage has a PSRR of -52 dB, but then the second stage amplifies everything it gets by the ratio R5/R11 and the PSRR at the output is just -28 dB.

Combining the coil damping and amplifier input resistor is an interesting thing, something I played with on a fisher impulse like recycling design, helping avoid the input guard diodes slowing flyback. The problem is that with fast coils the optimal damping resistor value rises and makes for a higher input resistor than you'd want.

The next modification would be to apply Moody's variable damping circuit so that the input resistor is high during most of the transient but then drops to about 500 ohms at the end. This has the benefits of faster decay (larger S/N ration) and lower noise and the drawback of a sensitive adjustment that would have to be performed by the MCU.

The output seen by the ADC sampler should look like this:

[ODM]

It's a novel design, but for the following effects I can't agree that this amplifier will behave indepently of noise riding on battery voltage.
* The ADC is tied to a fixed reference based on the logic voltage ground.
* Supply noise on the negative rail will affect the constant current drives.
* The JFET input amplifier is referenced to -Vbatt*(5/7), and this is multiplied by a gain of feedback resistor and equivalent of voltage divider, which means the PSRR is -24dB! I suggest coupling this stage with a decent capacitor to the reference of the previous stage, preferably no ceramics or failing that a good quality NP0 since it's a signal carrying cap.

Battery voltage will display a slow recovery after brief current pulses like PI transmit. Fortunately it can be constant enough not to show up in actual performance but driving a loudspeaker or headset can couple to the detector via battery voltage through this insidious means.

Can you run an AC analysis on your circuit with the reference signal riding on battery voltage, and a time domain analysis with a 10ns risetime squarewave riding on battery voltage? These are usually good tests for suggesting where attention to supply is needed.

Combining the coil damping and amplifier input resistor is an interesting thing, something I played with on a fisher impulse like recycling design, helping avoid the input guard diodes slowing flyback. The problem is that with fast coils the optimal damping resistor value rises and makes for a higher input resistor than you'd want.

[Qiaozhi]

I would welcome suggestions on how to interface the amplifier with the MCU's ADC.

One method I've used successfully in the past (where the opamp output swings between +/-5V) is to split the opamp output into two channels, where each channel is a precision rectifier. https://en.wikipedia.org/wiki/Precision_rectifier
One channel allows the positive part of the signal through, and the second channel passes the negative portion. If you make the negative channel inverting, you now have two signals which go from 0V to +5V. Feed these signals into two separate ADC inputs on the PIC. Then it's a simple task to combine these two inputs in software.

[Teleno]

I would welcome suggestions on how to interface the amplifier with the MCU's ADC.

For a 12V supply:

- The preamp's output is 6V - 7V and is passed on to the OpAmp non-inverting input.

- The OpAmp's output can swing between 3.8V - 8.2V = 4.4V (AD8610) and passed on to the ADC of the MCU.

- The MCU is powered at 5V.

So the problem is to adapt the 3.8V - 8.2V of to OpAmp to the 0V - 5V of the MCU.

One solution is to create a floating digital ground at about 7V for the MCU. But then the maximum swing at the ADC input would be 7V - 8.2V = 1.2V instead of the 5V that could be achieved.

Another solution is a a floating digital ground at 3V and a regulated rail at 8V. Then the OpAmp's output can cover most of the ADC input range.

Finally, a rail-to-rail JFET OpAmp can be used that's as least as fast as the AD8610 (List here). Then a simple LM78L05 regulator would power the MCU.

(P.S. AD8065 for $5 looks good- 7nV noise. AD8033 is $5 but 11nV noise. AD8067 is $6 with 6.6nV noise and 640uV/s slew rate. All in SMD packages only).

As a last resort the OpAmp can be scrapped and a discrete second stage be used (see my first version of the amplifier) in which case we're also served with an LM7805.

[Teleno]

Point taken on mixing threads.

The micro will have some fancy filtering afound it and careful ground plane placement. Can I suggest you design with an Analogue ground and a Digital ground then I can star the analogue ground an bring the main feed back to the battery connection point.

The digital and analogue grounds have to be the same because the ADC input of the MCU must be referenced to the same ground as the amplified signal. This ground is the OUT terminal of the LM79L05.

I will publish a more detailed schematic later.