DEEPER PI DETECTION DEPTH

[Aziz]

If we look at the power consumption, Sawtooth 2.4W x 17.3W Flattop, the answer looks easy. With even half the power consumption, the Sawtooth will give a much higher target response.

Then there is another advantage of the sawtooth, higher PPR, that allows for stacking or integration more samples, which gives a S/N advantage.

In short, Flattop is a waste of energy and time.

Tinkerer

Hi Tinkerer,

that was the direction, I wanted the discussion to go.
(don't waste expensive battery power)

Putting the t-on time towards the "linear" region (t-on << TC) and increasing the pulses per second rate (PPS). Then "collecting" all the spectral energy of the response for the whole time (t-on + t-off periods).
Even the current does not achieve a significant level (compared to the longer t-on period), but it gives a higher dI/dt particularly during the on-time.

While doing this, low inductivity coils could be used with high PPS rates (6k - 12k or more). The high pulse frequency is far away from the low frequency noise sources as well (50/60 Hz mains hum).

Well, it's coming into the region of the VLF detector principles. Except, we have a wide band frequency response.

Aziz

[Tinkerer]

Good work Qiaozhi. You've nailed down the main issue, zero ESR parasitic capacitance in the inductance model. Pretty sloppy work on LT's part.


I'm not sure that Carls work has conclusively proved it. He's only tested two targets both of which may have had time constants too long to reach 'saturation'. Carl's experiment is actually consistent with longer TC targets in Tinkerers model so it could still hold true.

The 2 samples that Carl used are fairly good representative targets. A Nickle with a very short TC and a silver dollar with a TC of more that 200us.

So, why do the simulations show different?

One of the reasons I could think of, is that the simulation uses an ideal "ring target". A coin is not an ideal target. The eddy currents are not uniform.

To verify the accuracy of the simulation, rings of short and long TC's would have to be used.

Is it worth wile?

Deeper understanding and better knowledge are always worth it.

When we are interested in target ID, like for de-mining or UXO, we want to thoroughly understand the reasons why a certain target responds differently from another target, be the difference in shape or metal alloy or caused by a different back ground matrix.

Morale of the story?

We need to design a simulation target model that can reproduce all the variations that real targets could present.

Big job.

Suggestions of how to design this universal simulation target model?

Tinkerer

[Tinkerer]

That's right. For the same pulse width of 100µs in his example.

What I intend to ask is, whether the almost "linear" region of the TX current ramp gives more benefits than the saturated region.

This requires a new question of course.

Aziz

If we look at the power consumption, Sawtooth 2.4W x 17.3W Flattop, the answer looks easy. With even half the power consumption, the Sawtooth will give a much higher target response.

Then there is another advantage of the sawtooth, higher PPR, that allows for stacking or integration more samples, which gives a S/N advantage.

In short, Flattop is a waste of energy and time.

Tinkerer

[Midas]

This in fact compares well with reality, except that the use of an ideal capacitor in series with the coil makes the glitches seem worse than they are in practice. In some simulations I ran, it was possible for the glitches to reach peaks of current as high as 60A.

In conclusion, we just need to be careful when using the LTSpice inductor model, and to be aware that any current measurement you add to the plot pane [labelled I(L1), for example] does not represent the current flowing in a single component, but rather the overall equivalent network.

Good work Qiaozhi. You've nailed down the main issue, zero ESR parasitic capacitance in the inductance model. Pretty sloppy work on LT's part.

I though we had already determined the answer to this particular question.
Carl did some comparisons on a real circuit, and posted the results in #137 ->
http://www.geotech1.com/forums/showp...&postcount=137

I'm not sure that Carls work has conclusively proved it. He's only tested two targets both of which may have had time constants too long to reach 'saturation'. Carl's experiment is actually consistent with longer TC targets in Tinkerers model so it could still hold true.

[Aziz]

I though we had already determined the answer to this particular question.
Carl did some comparisons on a real circuit, and posted the results in #137 ->

http://www.geotech1.com/forums/showpost.php?p=143025&postcount=137

That's right. For the same pulse width of 100µs in his example.

What I intend to ask is, whether the almost "linear" region of the TX current ramp gives more benefits than the saturated region.

This requires a new question of course.

Aziz

[Qiaozhi]

PS: The question:
The flat-top (t-on > TC) versus (almost) "linear" current ramp (t-on < TC).
What is better and why?

I though we had already determined the answer to this particular question.
Carl did some comparisons on a real circuit, and posted the results in #137 ->

http://www.geotech1.com/forums/showpost.php?p=143025&postcount=137

[Aziz]

BTW,

I don't expect a good explanation and proof of the above IQ award. I just want to stimulate a good discussion and hopefully someone will find a good solution or a good idea. The discussion should lead to a better understanding of the matter and should generate new ideas as well.

Feel free to talk about the above dark matter. Dark energy? Dark magnetics? Dark pulse? (Yeah, that's it!)



BTW, I don't know the answer yet!

(Do you feel better now?)

But the question is really good. We should knock it out.


Aziz

PS: The question:
The flat-top (t-on > TC) versus (almost) "linear" current ramp (t-on < TC).
What is better and why?

[Aziz]

IQ Award

Hi guys,

ok, the glitch problem isn't a real problem. Let's leave it and focus to the interesting dark matter.

The flat-top (t-on > TC) versus (almost) "linear" current ramp (t-on < TC).
What is better and why?

(Why dark matter? Well, that's a modern way to say "Damn it, I don't know!" )

The winner of the IQ award will gain high respect and reputation. So don't hesitate to contribute. Good luck.

Cheers,
Aziz

[Qiaozhi]

I cascoded the NMOS and the glitch remained, so I'm doubtful that it is CDG feedthrough. Interesting.

If I lower the gate resistor from 100 to 10 ohms in the simulation, I get a similar result to your scope picture.

[simonbaker]

OK - I understand what you were doing now. Yes, now I can see they're the same.
By the way, if you rotate the resistor by 180 degrees and replace it, the current plots can be overlaid with the correct polarity. Actually, the correct way to do this in SPICE is to use a zero-volt voltage source. Make sure you place it with the positive terminal on the left.
It certainly looks like we've found the real source of the problem. Good job!

I just plot -I(R6) to overlay them. But I like rotating the resistor better!

I wondered what the best way was! I'll try to remember zero-volt voltage source next time. Thanks!

-SB

[Carl-NC]

I cascoded the NMOS and the glitch remained, so I'm doubtful that it is CDG feedthrough. Interesting.

[Qiaozhi]

Thanks Qiaozhi,

C9 across inductance and coil resistance, definitely represents better the parasitic capacitance.

There is just one problem left: The glitch on Carl's real circuit.

Tinkerer

I don't think the simulation disagrees with the real circuit. In reality there will be a parasitic capacitance across the coil, but it also has an equivalent series resistance. That resistance is not modelled in the inductor network, and this makes the glitches look worse than they really are in practice.

The large glitch in Carl's plot is most likely caused by Miller effect, as pointed out by Midas several posts back. This seems to be a different issue.

[simonbaker]

Thanks Qiaozhi,

There is just one problem left: The glitch on Carl's real circuit.

Tinkerer

Why is that surprising?

-SB

[Qiaozhi]

Qiaozhi:

Did you measure the current through the .0000001 resistor and compare that to the current through the lumped coil?

That was the point -- you can't compare coil currents, because LTSpice treats the lumped coil as a 2-port RLC network and displays the port current (I believe), not the current in the ideal inductor. So to compare apples to apples, you have to compare the current into the discrete RLC network (using the .00000001 resistor as a "wire") and compare to the lumped coil current.

Maybe I didn't get your point though (it happens ).

-SB

OK - I understand what you were doing now. Yes, now I can see they're the same.
By the way, if you rotate the resistor by 180 degrees and replace it, the current plots can be overlaid with the correct polarity. Actually, the correct way to do this in SPICE is to use a zero-volt voltage source. Make sure you place it with the positive terminal on the left.
It certainly looks like we've found the real source of the problem. Good job!

[simonbaker]

Ok,

the lumped and simplified LTSpice inductor model seems to work bad. Use the discrete solution (L, Rs, Rp, Cp model). If you add all the currents I(L)+I(Cp)+I(Rp), then you get exactly the same current of the lumped model.

Aziz

Problem solved. Next problem.

Yes, that's what I'm saying too. I don't think that is a problem with LTSpice -- it simply treats the lumped inductor as a two-port network and measures the total current into (and out of) the ports -- it doesn't measure what goes on inside when you ask for the inductor current. That's what I would expect.

-SB