New Bipolar Boost TX and Front End

[Mdtoday]

While working with the menu's I made a discovery... the values reported by the RX XADC were all positive in reference to ground. What we want is + and - revolving around the midpoint (0.5V at the FPGA pin). With no connection, the reported value should be a large negative number, but were actually around 0. I was under the assumption that by declaring the input channel as bi-polar, that the conversion process would be + and - around the reference midpoint. I WAS WRONG... the bi-polar declaration just changed the way that the input channel was configured to be measured... not the conversion. To correct this, the XADC IP was re-configured with the bipolar setting of the channel set to OFF. Also adjusted the output of the RX data to the midpoint by subtracting 2048 from the 12-bit data.

Now when the RX pre-amp output reference is correctly set to ~1/2 of the 20V pre-amp Vcc, the output value of the RX data should be ~0. By calculating the divider network supplying RX signal to the Cmod-A7 (16k ohm), a pre-amp output of 9.66V should be ~ zero RX digital voltage from the RX FPGA module.

I plan on implementing a couple of displays for the "Maintenance" menu to assist in manually tuning the RX reference and the damp delay. One display will display the decimal value for the filtered Sample 1 with TX turned off. This will facilitate adjustment of the RX reference value. The goal will be to adjust as close as possible to 0. The other planned display will display whether S0 is positive or negative with TX turned on. This will facilitate manual tuning of the damp delay. Here you would manually increase the damp delay until S0 is negative and then decrease the delay until it flips to positive.

The menu system is not yet functional as I am rewriting it to be completely interrupt responsive. But if an operational TX-RX board set is connected, the current debug messages will display the received values from the RX and filter modules.

Excellent work JL! thanks for sharing and I like the idea of a maintenance menu, very helpful. I just need to install the inductors and check mosfet gate voltages, install the mosfets and I should have a working board set.
Currently, I am just working on the internal wiring length drawing and hookup diagram and also printed a version of the enclosure that has a top hatch like this just for ease of access and as an aid to get the wiring lengths right.
I'll be post up a drawing and photos once completed.

[KingJL]

RX Xadc Implementation Change

While working with the menu's I made a discovery... the values reported by the RX XADC were all positive in reference to ground. What we want is + and - revolving around the midpoint (0.5V at the FPGA pin). With no connection, the reported value should be a large negative number, but were actually around 0. I was under the assumption that by declaring the input channel as bi-polar, that the conversion process would be + and - around the reference midpoint. I WAS WRONG... the bi-polar declaration just changed the way that the input channel was configured to be measured... not the conversion. To correct this, the XADC IP was re-configured with the bipolar setting of the channel set to OFF. Also adjusted the output of the RX data to the midpoint by subtracting 2048 from the 12-bit data.

Now when the RX pre-amp output reference is correctly set to ~1/2 of the 20V pre-amp Vcc, the output value of the RX data should be ~0. By calculating the divider network supplying RX signal to the Cmod-A7 (16k ohm), a pre-amp output of 9.66V should be ~ zero RX digital voltage from the RX FPGA module.

I plan on implementing a couple of displays for the "Maintenance" menu to assist in manually tuning the RX reference and the damp delay. One display will display the decimal value for the filtered Sample 1 with TX turned off. This will facilitate adjustment of the RX reference value. The goal will be to adjust as close as possible to 0. The other planned display will display whether S0 is positive or negative with TX turned on. This will facilitate manual tuning of the damp delay. Here you would manually increase the damp delay until S0 is negative and then decrease the delay until it flips to positive.

The menu system is not yet functional as I am rewriting it to be completely interrupt responsive. But if an operational TX-RX board set is connected, the current debug messages will display the received values from the RX and filter modules.

The current project archive is Vivado_BiPolar(11-8-2019).zip .

The change log:
Change Log.txt

The current FPGA design:

[KingJL]

LtSpice Simulation Broken

A recent update to LtSpice has broken the simulation of the Bipolar TX and Front End. The LtSice simulation files are available in post #4 of this thread. LtSpice changed the symbol layout of the LTC1693-1 and LTC1693-2 so that the connections are no longer valid. Basically what they did was to move the Vcc1 and Vcc2 connections to the top side of the symbol and the GND1 and GND2 to the bottom side of the symbol. The In1, In2. Out1, and Out2 spacing has been changed, but the relative positions were NOT changed. Edit those connections to U6, U7; double click X1 and edit U1 of the sub-module; save everything and you should be good to go.

I would post a new zip file for the simulations, but that would break simulations for those whose LtSpice has not been updated. The LtSpice update changed the affected symbols when they updated the internal Linear Technologies device library files.

[KingJL]

... Was going thru all pages of your work but couldn't find the schematic. I wanted to test Bipolar Tx, have already tried H bridge but capacitance doesn't seem to go well with performance.

The schematic, both LtSpice and Kicad files (including a pdf of Kicad sch) are within the 1st 25 posts of this thread. Post #15 would be a good source for the Kicad schematic info. Post #4 for the LtSpice info.

[KingJL]

... I will also speak with one of my suppliers and see if we can get some Belden 2222.

I may have identified what may be a more suitable cable... at least it appears to be readily available... Belden 8729.

For mono coil cables, I would like to try Belden 1800F.

[soultech]

Hi KingJL, Your work is commendable. I am surprised how can you single handedly do electronics, embedded system and 3D desining :-) Was going thru all pages of your work but couldn't find the schematic. I wanted to test Bipolar Tx, have already tried H bridge but capacitance doesn't seem to go well with performance.

[Mdtoday]

After considerable thought, I like "Alternatively, stay with the 5 pin and run separate shields for TX/RX and joint at the coil connector like this Coil connector PCB.JPG".

If I can find a source, I would like to try Belden 2222 for IB coil cable. The conductor to conductor capacitance seems reasonable at 18 pF/ft.

Yes, I agree, stay with the 5 pin, I will make the changes.

I will also speak with one of my suppliers and see if we can get some Belden 2222.

[KingJL]

I am not happy with the Coil connector board for use with isolated RX/TX coils and will re-do the layout as the fix for the current board is more of a hack.
As stated earlier, its still fine for mono coils. The pin out is a standard ML mono connection.
I will post the corrections and Kicad files in due course.
JL, I'm thinking we could just go with a 6 pin plug, same style as the 5 pin and use 3 each for TX and RX. That would be TX shield, TX+,TX-, RX shield, Rx+, RX-.
Alternatively, stay with the 5 pin and run separate shields for TX/RX and joint at the coil connector like this [ATTACH]48248[/ATTACH]

What are your thoughts on this?

After considerable thought, I like "Alternatively, stay with the 5 pin and run separate shields for TX/RX and joint at the coil connector like this Coil connector PCB.JPG".

If I can find a source, I would like to try Belden 2222 for IB coil cable. The conductor to conductor capacitance seems reasonable at 18 pF/ft.

[waltr]

18-20 bits with some pre-amp gain sounds about right.
If I remember right, you are then passing the samples through a filter. If doing this on multiple cycles the noise should drop and effextive bits increase.

I have been experimenting with a PIC32 digitizing a 500x (54dB) pre-amp (same front end circuit as Hammer Head) into the PIC's 10bit ADC at 2usec per.
I add 8 cycles as an average and to boost effective number of ADC bits. Seems to work fine and noise I fight is coming out of pre-amp.
Has been interesting experiments to then obtain Target TC, threshold triggering, etc in software.

[KingJL]

Be aware that this LTC2380-24 does go into a bad state if the +input is over Voltaged and at least 256 conversions are done.
The very first run of this ADC also had a silicon bug that caused random Noise for the first 256 conversions. I run into these problems using this ADC for instrument design at work.
It does have a build in filter to average 2^x samples. This can be handy if the real sample rate does not need to be fast but If you are digitizing the decay I don't see any need.

A big issue may be getting circuits with low enough noise to take advantage of 24 bits. Typically it is hard to get circuit noise low enough for even 16 bits especially if signals are coming from a detector coil that is also an antenna. Your full differential circuits should help considerably but still may not be enough to take advantage of 24 bits.

There is the LTC2378-20, a 20 bit ADC that is a drop in to the LTC2380-24 and it does not have the built in filters.
This may be a better option

The design, hardware and firmware/PLD is a bit beyond what I can do but have enjoyed following.
Can't wait for real in field testing reports.

@waltr, Thanks for the tip on the LTC2378. I will research that item!

A big issue may be getting circuits with low enough noise to take advantage of 24 bits. Typically it is hard to get circuit noise low enough for even 16 bits especially if signals are coming from a detector coil that is also an antenna. Your full differential circuits should help considerably but still may not be enough to take advantage of 24 bits.

Totally agree with what you stated. In the past I created a PMOD board using the TI ADS8881 18 bit ADC for use with the SPARTAN 6 FPGA. The 18 bits were adequate for use in a PI detector and provided acceptable sensitivity and dynamic range. But I feel that 18 bits is the bare minimum for acceptable performance as it still required about 36 db (64x) pre-amp gain to maximize sensitivity (at the expense of some dynamic range). I think 20 bits should be ideal. I could set the gain of the diff input pre-amp stage to 4x and the second pre-amp stage (opa828 ) at 4x with out any other changes to the TX/RX board. With a total of 16x (24 db) pre-amplification, I cannot see a dynamic range limitation of any signals that should be encountered.

Thanks again for your input!!!

[waltr]

The next step after this is proven is to use 2 opa828's configured as a low gain ( <= 10 ) differential input 2 op-amp instrumentation amplifier (with pseudo log limiting) feeding an LTC2380-24 ADC circuit.

Sounds like a great plan and the LTC2380 is a good device.

Be aware that this LTC2380-24 does go into a bad state if the +input is over Voltaged and at least 256 conversions are done.
The very first run of this ADC also had a silicon bug that caused random Noise for the first 256 conversions. I run into these problems using this ADC for instrument design at work.
It does have a build in filter to average 2^x samples. This can be handy if the real sample rate does not need to be fast but If you are digitizing the decay I don't see any need.

A big issue may be getting circuits with low enough noise to take advantage of 24 bits. Typically it is hard to get circuit noise low enough for even 16 bits especially if signals are coming from a detector coil that is also an antenna. Your full differential circuits should help considerably but still may not be enough to take advantage of 24 bits.

There is the LTC2378-20, a 20 bit ADC that is a drop in to the LTC2380-24 and it does not have the built in filters.
This may be a better option

The design, hardware and firmware/PLD is a bit beyond what I can do but have enjoyed following.
Can't wait for real in field testing reports.

[Mdtoday]

Bit more work on the internal wiring layout.
It is still in draft form.
[ATTACH]48246[/ATTACH]

Kicad File [ATTACH]48247[/ATTACH]

I will update again soon.

While doing this layout, I did realise a problem with the Probe/coil connector PCB.

It is fine for Mono coil use but requires a track cut between the 2 RX pins on the 5 pin connector for use with DD or concentric.
The zero ohm links were meant to cater for this but I messed up. Still it's an easy fix, just annoying that I missed it.

I am not happy with the Coil connector board for use with isolated RX/TX coils and will re-do the layout as the fix for the current board is more of a hack.
As stated earlier, its still fine for mono coils. The pin out is a standard ML mono connection.
I will post the corrections and Kicad files in due course.
JL, I'm thinking we could just go with a 6 pin plug, same style as the 5 pin and use 3 each for TX and RX. That would be TX shield, TX+,TX-, RX shield, Rx+, RX-.
Alternatively, stay with the 5 pin and run separate shields for TX/RX and joint at the coil connector like this

What are your thoughts on this?

[Mdtoday]

Bit more work on the internal wiring layout.
It is still in draft form.
KingJL_Bipolar_TX_Wiring.pdf

Kicad File KingJL_Bipolar TX wiring.zip

I will update again soon.

While doing this layout, I did realise a problem with the Probe/coil connector PCB.

It is fine for Mono coil use but requires a track cut between the 2 RX pins on the 5 pin connector for use with DD or concentric.
The zero ohm links were meant to cater for this but I messed up. Still it's an easy fix, just annoying that I missed it.

[Mdtoday]

You can try the ~320uH TX, but preliminary experimentation seems to indicate that < 500uH starts to lose to much boost. I am hoping to see the opposite effect of > 500uH with a good compromise of speed and exceptional boost being in the range of 750uH... we'll see.I really don't expect any real gains in sensitivity with the current preamp/ADC configuration (mainly due to the minimum sensitivity granularity limitation of the 12 bit ADC). This design is mainly to prove and exploit the benefits of FPGA concurrency and upc interrupt driven processing to achieve all desired DSP. The next step after this is proven is to use 2 opa828's configured as a low gain ( <= 10 ) differential input 2 op-amp instrumentation amplifier (with pseudo log limiting) feeding an LTC2380-24 ADC circuit. There is enough room on the I/F board for the 2380 and reference circuit by getting rid of J3 and J6 (which are currently unused and not needed). I would expect this configuration to have significant performance/dynamic range benefits. There is not much change to the FPGA HDL and software design as I have already allowed for a 24 bit Rx. But that version will have to wait until after the next spring household move to the Florida panhandle gulf coast.

Sounds like a great plan and the LTC2380 is a good device.
I will try the 320uH coils at some stage but wind a new coil to suit your baseline design.

KingJL_Bipolar_TX_Internal Wiring_A.pdf
Here is a draft view of the internal power wiring, need to add probe board and then a sanity check, I will post the Kicad file later today.

[KingJL]

On the coils, thanks for the information, I have a few different coils but with a max of 450uH RX and 320uH TX concentrics. I planned on building some more to suit this project so it is good to have the baseline info.

You can try the ~320uH TX, but preliminary experimentation seems to indicate that < 500uH starts to lose to much boost. I am hoping to see the opposite effect of > 500uH with a good compromise of speed and exceptional boost being in the range of 750uH... we'll see.

It will be interesting to see what gain is arrived at for the OPA828, a balancing act for sure.

I really don't expect any real gains in sensitivity with the current preamp/ADC configuration (mainly due to the minimum sensitivity granularity limitation of the 12 bit ADC). This design is mainly to prove and exploit the benefits of FPGA concurrency and upc interrupt driven processing to achieve all desired DSP. The next step after this is proven is to use 2 opa828's configured as a low gain ( <= 10 ) differential input 2 op-amp instrumentation amplifier (with pseudo log limiting) feeding an LTC2380-24 ADC circuit. There is enough room on the I/F board for the 2380 and reference circuit by getting rid of J3 and J6 (which are currently unused and not needed). I would expect this configuration to have significant performance/dynamic range benefits. There is not much change to the FPGA HDL and software design as I have already allowed for a 24 bit Rx. But that version will have to wait until after the next spring household move to the Florida panhandle gulf coast.