New Bipolar Boost TX and Front End

[KingJL]

schematic

Updated my Kicad schematic... now to redo the board layout.

Kicad schematic.pdf

[Mdtoday]

Just ran the sim and it works.
Question:
What do the X1-X4 devices do?
I open their schematic and they seem to be pulsed mosfet drivers.

Hi Waltr, yes they are and I believe derived from the Vallon Tx
I can’t find the link right now but KingJL did an excellent bit of reverse engineering and posted his findings in the Vallon thread some time ago well worth a look.

Cheers

MDtoday

[waltr]

Just ran the sim and it works.
Question:
What do the X1-X4 devices do?
I open their schematic and they seem to be pulsed mosfet drivers.

[Mdtoday]

Works fine now, thank you KingJL
Nice detailed work, well done.
I'll go play with it some more and report back, interesting circuits, it should make for a nice little compact circuit, thanks again for sharing.

cheers

Mdtoday

[Mdtoday]

Mdtoday, try this zip... it has the 74HC.lib. The IRFR320.sub isn't used and shouldn't be called. I can't find a .inc calling it in this version.

(Ahhh, found it in one of the test modules!!! added it to New Bipolar Boost(4).zip

Excellent, thank you KingJL, much appreciated, I'll go play with it now.

Mdtoday

[KingJL]

... Any timing info or just extract from the LTSpice sim.

Extract from the sim... should be somewhat easy as they are all parameterized. The design assumes a 10:1 ratio of PRT vs PW. All you have to do is change the PRT and the PW, damping, RX blanking, etc. automatically changes to the correct timing. I have tested PRT's in the range of 500 usec - 3000 usec.

One item that is critical to set up for optimum performance is the Dw parameter. This is the delay from TX off until where the damping is applied. If the pre-amp output is negative immediately after damping is applied, Dw is too large... you need to decrease it until the pre-amp output flips positive ( I literally mean flip, there is no gradual decrease to 0). Since my FPGA clock is set for 100 MHz, the minimum granularity of all timing adjustments is 0.01 usec. an increment of 0.01 usec past the optimum setting of Dw will cause the pre-amp output to flip negative immediately after damping is applied. Any change that changes the peak coil current will affect the optimum setting of Dw.

[waltr]

Wow, I will need to study, and run, this.
Any timing info or just extract from the LTSpice sim.

I have been working on using a PIC32 after the pre-amp to do everything.
Still using old Hammer-Head front end (TX & pre-amp). Have planned on doing new front end and your work looks promising.

Thanks for sharing and looking forward to you having a real circuit to test.

[6666]

Thanks

[KingJL]

I just tried running the sims and have the following errors.

Could not open include file 74HC.Lib
Could not open include file IRFR320.Sub

cheers

Mdtoday

Mdtoday, try this zip... it has the 74HC.lib. The IRFR320.sub isn't used and shouldn't be called. I can't find a .inc calling it in this version.

(Ahhh, found it in one of the test modules!!! added it to New Bipolar Boost(4).zip

[Mdtoday]

Hi KingJL

Thanks for sharing & nice work.

I just tried running the sims and have the following errors.

Could not open include file 74HC.Lib
Could not open include file IRFR320.Sub

cheers

Mdtoday

[KingJL]

New zip file (removed an unused ".inc" that would cause some complaints from LtSpice).

[KingJL]

I have been working on a new bi-polar boost TX and front end for about the last 9 months that can work with both mono and IB coils. My intent is for use with an FPGA to provide all timing signals and post processing of the pre-amp output. The deign was inspired by Dave J's US Patent US9366778 and some observations I made during the study of the VMH3CS methods and technologies. I am now satisfied with the behavior under LtSpice simulation and now am in the process of implementing the design in Kicad. Actually, I had the Kicad design and layout completed, but made some last minute changes that changed about 10% of the implementation. The "New Bipolar Boost.zip" file should include all of the needed files to run the LtSpice simulation of the "mono" mode. If LtSpice complains about any missing components, let me know and I will supply them.


zip file updated... was missing sym and sub for SPDT switch