New Bipolar Boost TX and Front End

[moorejl57]

I have been trying to follow the concepts in this thread and I have to admit I don't know what a bipolar TX means. I tried searching but no luck in finding an explanation. When I see bipolar, I think of how a stepper is driven with an H-Bridge, but I assume you are not talking about driving the main coil in both polarities.

[Mdtoday]

Like I said... I hope to verify the pulse transformer primary connections this week. But even if they are wrong, they can be corrected by changing the direction of the winding (since we are winding our own primary on the toroid). Have you used VHDL with defining FPGA functionality previously? If not there are a couple of quirks regarding changing and using values of signals and variables within a a process.

In your time JL, wasn't pushing you, what I meant was, I'll have another look over layout to see if I can spot anything else...
Yes I have coded with VHDL after moving from Verilog and been slapped more than a few times with similar things, I will keep that in mind.

cheers

Mdtoday

[KingJL]

Nice work JL, this is looking quite interesting, thanks for sharing.
I have just received the Artix 7 module so i can start playing.
[ATTACH]46510[/ATTACH]

Haven't had much time to check your TX PCBA again but will do, however last time I checked it looked Ok

cheers

MDtoday

Like I said... I hope to verify the pulse transformer primary connections this week. But even if they are wrong, they can be corrected by changing the direction of the winding (since we are winding our own primary on the toroid). Have you used VHDL with defining FPGA functionality previously? If not there are a couple of quirks regarding changing and using values of signals and variables within a a process. When you change the value of a signal within a process, the value is not really changed until the current process cycle is completed (the change can be observed during the next entry into the process). A change of value of a process variable is in effect immediately. That little quirk has bitten me more than once.

[Mdtoday]

Nice work JL, this is looking quite interesting, thanks for sharing.
I have just received the Artix 7 module so i can start playing.


Haven't had much time to check your TX PCBA again but will do, however last time I checked it looked Ok

cheers

MDtoday

[KingJL]

New Bipolar_TX version... added MPP

... The Vivado project files are in a zip at this link.
https://drive.google.com/file/d/1A0Y...ew?usp=sharing

New Bipolar TX version (5-28-2019)... new link: https://drive.google.com/file/d/1Rw6...ew?usp=sharing

While visiting the NC coast last week, I had a brainstorm. What about the option to transmit two different pulse widths. So I coded in the capability to transmit one wide TX pulse (one half PRT) pulse followed by 4 bipolar pulses of normal pulse width. This maintains the bipolar nature of the TX. The capability will be controlled by the input MPP_i (Multiple Period Pulse) being held high. In the tested example the PRT is set to 500 usec, S1=10usec, S2=20usec, s3=40usec, MPP=1. This resulted in a positive cycle (TXA) of a 250 usec pulse followed by 4 cycles (starting with a negative (TXB) cycle) of 50 usec pulses which is followed by a negative cycle (TXB) of a 250 usec pulse followed by 4 cycles (starting with a positive (TXA) cycle) of 50 usec pulses. This results in an average duty cycle of 18% with MPP vs. the normal 10% duty cyle.



I have updated the link for the zip containing the current Vivado project files and included a text file of the VHDL code for those that cannot view the Vivado project files. Hopefully, I will get the testing/verification of the pulse transformer connections completed this week.

[Mdtoday]

The TX module will be modified slightly (in the future) to accommodate a sample immediately after RX un-blank to test for optimum time for start of damp:

Need to have an initial sample (SMP0) to sample the RX immediately after the RX un-blanking to test for pos or neg to tune the optimum time before damp. If neg, then damp must occur earlier. The ideal setting is to delay damp until signal flips negative and the back up until it flips positive.

This sounds like a good idea

cheers

Mdtoday

[Mdtoday]

I still need to verify the toroid connections... will be out of town next week, so it will probably be after June 1st.

Thanks for the heads up, I’ll spend a bit of time on the tool chain then and perhaps look over the board again.

[KingJL]

The Vivado project files are in a zip at this link.
https://drive.google.com/file/d/1A0Y...ew?usp=sharing

The TX module will be modified slightly (in the future) to accommodate a sample immediately after RX un-blank to test for optimum time for start of damp:

Need to have an initial sample (SMP0) to sample the RX immediately after the RX un-blanking to test for pos or neg to tune the optimum time before damp. If neg, then damp must occur earlier. The ideal setting is to delay damp until signal flips negative and the back up until it flips positive. The code in TX timing will be changed to effect this after the RX module is developed with handshking with the TX timing module.

[KingJL]

Nice work JL, I look forward to trying out the Vivado project files, thanks for sharing.

I should have the FPGA board in a couple of days so will be interesting to check it all out.
I have most components for the Bipolar TX PcBs but haven?t ordered the blank boards yet but will do after I play around with the FPGA and Vivado.

cheers

MDtoday

I still need to verify the toroid connections... will be out of town next week, so it will probably be after June 1st.

[Mdtoday]

The CIC filter delay equation is in error (I made a huge mistake on transposition)... the correct delay for the CIC filter is T = (R-1)/(2*Fs) * N. The delay for our design CIC filter (Fs=2000, R=10, N=5) is 11.25 ms, resulting in a combined delay of 48.25 ms or 90 samples. This combined filter provides an attenuation (noise floor) of about -60db for anything outside the passband of 0 - 40 Hz.

Nice work JL, I look forward to trying out the Vivado project files, thanks for sharing.

I should have the FPGA board in a couple of days so will be interesting to check it all out.
I have most components for the Bipolar TX PcBs but haven’t ordered the blank boards yet but will do after I play around with the FPGA and Vivado.

cheers

MDtoday

[KingJL]

Could someone help could not open include file "spdt . sub" what do I need to do? Tried to open .sub file, don't know what to do with it. Why do I have to reenter all my pass words after clicking on a .sub file? Not a computer person.

Change the extension from .txt to .sub. You never want to double click a .sub (or a .mod or lib file for that matter). If you want to view the contents right click and select "open with" and the select a suitable editor (notepad, worpad, etc.). Put the .sub file in the working directory of your current schematic or put it in the "LTSPICE".../lib/sub directory.

NOTE: the spdt.sub file was included in the zip of post #4 of this thread.

[KingJL]

To be more precise from the generalized previous answer...I have located the calculations for group delay through the filters. The group delay is basically the time from when a change is introduced into the filter until the effect is seen in the output assuming the change is within the passband of the filter. The group delay can be expressed in time or phase. These formulas calculate the group delay in time. For the CIC filter the group delay in seconds is T = 1/(((R-1)/2) * N) where N = filter order and R = rate change (decimation factor). For the FIR the group delay is T = (taps-1)/ (2 * Fs). For our 5th order CIC with a rate change of 10 and an input Fs of 2000, the delay is 44 ms. For our compensation fir with 16 taps and an input Fs of 200, the delay is 37 ms. So the combined group delay for the complete filter is 81 ms. Or another way to view it, is that after 162 samples at our operating frequency of 2000 pps, the integrated output will start appearing above the noise floor of the filter.

The CIC filter delay equation is in error (I made a huge mistake on transposition)... the correct delay for the CIC filter is T = (R-1)/(2*Fs) * N. The delay for our design CIC filter (Fs=2000, R=10, N=5) is 11.25 ms, resulting in a combined delay of 48.25 ms or 90 samples. This combined filter provides an attenuation (noise floor) of about -60db for anything outside the passband of 0 - 40 Hz.

[green]

Could someone help could not open include file "spdt . sub" what do I need to do? Tried to open .sub file, don't know what to do with it. Why do I have to reenter all my pass words after clicking on a .sub file? Not a computer person.

[KingJL]

Vivado project files

You can upload it too Google Drive. Zip size is too high for most email providers as well.

Thank you!!

The Vivado project files are in a zip at this link.

https://drive.google.com/file/d/1A0YisaYbuZ7ZteOK6csL8rjizVdb2iC9/view?usp=sharing

[eclipse]

You can upload it too Google Drive. Zip size is too high for most email providers as well.