Goldscan 5 - What is the purpose of the CD4001 ?

[greylourie]

Hello all.

I am struggling to understand a basic element in this design.
I was looking at the schematic for the Goldscan 5 posted here . Click the "here" to take you to the posted pdf schematic. On page 2 you can see the configuration of the CD4001. It seems to feed in after the comparator amp.



Is it supplying a pulse to the circuit ? Does it also have influence on the feedback of the channel B LT114 ?

[Jose]

I think it is an automatic reset which acts each time you turn the detector.
Jose

[kt315]

yes, some kinda a reset on turn-on of hold-and-store-circuit, ie SAT. you can see this part in GS-IV sch, where it is released like a push knob.

[greylourie]

Hi Jose

Thank you for replying. Do you mean that it acts to reset the threshhold ?

[greylourie]

yes, some kinda a reset on turn-on of hold-and-store-circuit, ie SAT. you can see this part in GS-IV sch, where it is released like a push knob.

Cheers kt315.
I saw your answer after replying to Jose.

[yoda]

It's a mute circuit with a turn off delay. The 4001 NAND is wired as an inverting buffer. When power is applied, the input of the buffer circuit is low because of the 1uF cap's discharge state, driving the buffer circuit output, high. This causes the JFETs, J113 to turn on, muting the signal inputs of the op amps. As a bit of time goes by, the 1uF cap gradually charges, driving the buffer circuit output, low, causing the JFETs, J113 to turn off, allowing signal to pass through the op amp stages. This is probably there to prevent some kind of nasty audio happenings during power up. --Ed

[yoda]

I just had a look at the schematic. While this is a mute circuit as I describes, seems as though there should be a mute signal going to the input of the 4001 circuit at TTL level. Typically, when TTL and cmos are connected, an interfacing pull up resistor is connected as shown. Unless there is some type of resistance across C, C will not discharge at an appreciable rate. Discharging of the 1uF cap is necessary to act as a delayed mute "power on" circuit, as I described. There must be a mute line which was omitted.--Ed

[kt315]

some people does not want and do not wish to see SAT circuit in a schematic. so for example they easily did throw out the SAT from Barracuda and Surf PI schematic.
they consider this part needless while original bara schematic HAS a reset of SAT, surf pi HAS tuning SAT part , but in the schematic with mods. why people are so blind it is mistery...

[satdaveuk]

some people does not want and do not wish to see SAT circuit in a schematic. so for example they easily did throw out the SAT from Barracuda and Surf PI schematic.
they consider this part needless while original bara schematic HAS a reset of SAT, surf pi HAS tuning SAT part , but in the schematic with mods. why people are so blind it is mistery...

Hi
Maybe I got the wrong end of the stick'
My Barracuda builds were from the original hand drawn circuit and hand written parts list, The difference on my second build was all semiconductors were socketed so I could easily convert to silverdog design which as we all know was modified to an extent that it functioned like the surf project.
What brought you to my attention was are you actually saying that there's more to the hand drawn Barracuda circuit than is actually shown here or are you commenting about the bought in a bag modified kits from silverdog.
Regards

[sinclairuser]

i thought it was the battery test/charge circuit that was omitted, what else is missing?.

[greylourie]

What I was really interested in, (and was the reason I posted only the circuit and not its final destination) was the mechanism of HOW it worked. Datasheet says CD4001 comprises of NOR gates.

By making the inputs common (tied together) on each NOR, it becomes a NOT. What happens when 3 x NOT gates are chained to each other ? Any input on first one results in opposite on the last one.

Some kind of oscillator ? Does it run continually ? Does the capacitor/resistor cycle an off/on state onto the input to the first NOT ?

[golfnut]

At power up the cap draws current as it charges and almost grounds the cold side of the resistor. This logic 'low' on the cap, is a 'High' at the buffered output end.

When the cap is charged it stops taking current and has Vbatt across it. This high volts is inverted to a logic 'low' at the output end.


So its a vanilla active high reset pulse generator.

[greylourie]

Thanks golfnut,

With your explanation, what Jose' said above makes sense to me now.