Impuse inspred flexible TX and RX-FE platform

[KingJL]

While balancing the 10" concentric coil and subsequent quick tests to see the coils functioning, I have come to the following conclusion.. balanced IB mode, is where this platform is going to shine. The time while the coils current is collapsing shows the highest signal sensitivity. These signals are gain jumper disconnected ( G=64 ).





Next step... get my FPGA platform and code the TX and ADC sample timings. Based on my simple visual observations, I feel confident that the 18 bit ADC and FPGA controlling 9 samples and 3 different 8 channel digital filters will yield superb sensitivity. Initially, I am going to allocate 4 sample channels to the falling coil current timeframe, and 4 sample channels to the traditional PI sample period (immediately after coil current ceases), and one sample for environmental cancellation taken 5 usec before the TX perioid.

[Chet]

Hi KingJL


I applaud you for your outstanding project and results. You have provided great documentation and oscilloscope shots.
I have a couple of questions. Will you use the falling current samples for discrimination? What amplitudes are the signal spikes/excursions that go off screen?
Thank you for sharing this project with us.


Have a great day,
Chet

[KingJL]

Will you use the falling current samples for discrimination?

Not sure yet... Discrimination per se... probably not. But general target charactaristics are definitely a possibility.

What amplitudes are the signal spikes/excursions that go off screen?

If you are talking about the vertical spikes on the blue trace, they are the leading/trailing edget of the coil voltage wave form. These edge can never be completely canceled out because of slight distortions to the rising/falling edges as seen in the three coil windings. Also, however slight, there is a minute time difference for the magnetic field of the main TX coil to reach the bucking coil for cancellation. The amplitude of the spikes is about 400 mv peak.

Thanks for the positive comments,
JLK

[andon80]

I congratulate these issues is a very nice circuit and VLF systems happen for both pi pi only does the system

[KingJL]

Ordered the FPGAdevelopment board(s) today...
http://www.xess.com/shop/product/xula2-lx25/
http://www.xess.com/shop/product/stickit-mb/

I ordered the LX25 version to insure that I have the resources to implement the hardware functions that I desire ( especially the DSP functions ). It may prove out that the LX9 may have the required resources, but that will not be proved until all is implemented.

The first 3 functios to design will be the TX timing, sample timing, ADC control (for my 18 bit ADC board... http://www.geotech1.com/forums/showt...Resolution-ADC ).

[KingJL]

Ordered the FPGAdevelopment board(s) today...
http://www.xess.com/shop/product/xula2-lx25/
http://www.xess.com/shop/product/stickit-mb/

I ordered the LX25 version to insure that I have the resources to implement the hardware functions that I desire ( especially the DSP functions ). It may prove out that the LX9 may have the required resources, but that will not be proved until all is implemented.

The first 3 functios to design will be the TX timing, sample timing, ADC control (for my 18 bit ADC board... http://www.geotech1.com/forums/showt...Resolution-ADC ).

The development of the FPGA PI implementation will be discussed in a separate thread ( http://www.geotech1.com/forums/showt...826#post217826 ) as the subject of the current thread has broader application possibilities. This will allow the discussion of this thread to remain relevent to the original subject.

[KingJL]

Testing of the platform with the FPGA has led to the addition of 1K pull-down resistors between the TX inputs and GND. This was easily accomplished by soldering these resistors between the input pins and GND on the bottom side of the board. The reason that these may be needed is that some devices (namely the XuLa FPGA board) may hold the device outputs high via internal weak pull-ups during programming and initialization. Needless to say, if the TX/RX platform is powered during this situation, both the TX1 and TX2 would be active at the same time... not good... can destroy the 2 TX transistors and the 2 TX voltage regulator transistors. The 1K pull-downs at the TX1 and TX2 inputs prevent this.