Target ID with simple F.E.T analogue multiplier?

[dbanner]

Would this circuit topology work for such a task. In this circuit, Vout is proportional to V1*V2. The F.E.T's conductance are matched to within+\-5%

Can the circuit can be tweaked for X and R channel inputs to give target information.

What do you think? This circuit is featured in Wireless world Circard collection 1978. All the relevant math is there.

[Altra]

I think you need some kind of division function to get a target vector. Multiplying X x R does not let you know which is greater or lesser. One of the early Tesoros used a analog multiplier IC for target ID. If you look at the datasheet these chips also had a division function that was used. Is there any text description with your circuit?.

[Skippy]

If it helps anyone:

Page 126 of this pdf shows the circuit ( plus others on previous pages ):
Circard Collection 1978 | PDF

There are some nifty things that can be done with analogue multipliers/dividers. I like the one that calculates the vector amplitude A = sqrt ( X*X + Y*Y )
There are some excellent design resources for these IC's out there, mostly older app books from the 70's / 80's, really interesting stuff.
Update:
This is one I have in print and pdf:
Nonlinear Circuits Handbook, 1976 | Analog Devices

[pito]

ATtiny85
VDI=degrees(atan2(Yy,Xy));
Magn = sqrt(pow(Xy,2)+pow(Yy,2));

[Aziraphel]

If it helps anyone:
Page 126 of this pdf shows the circuit ( plus others on previous pages ):
Circard Collection 1978 | PDF

https://www.scribd.com/document/6661...ollection-1978
not the best way to leave links here, leading to a paid site when in 0.2 seconds Google shows that you can download it without any fuss from the magnificent site worldradiohistory.com

[dbanner]

arctan(Y/X) = target ID angle.

In whites 5900/6000di they do log(A)+log(B) which is the same as log(A*B). I am not sure what is exactly is done in the stage following the summing amp. But after that it goes to the meter via a sample switch.

In the toltec, RC4200 is used as voltage divider I think, Therefore input pin 8 divided by input pin 5. Pin 4 is the output. pin 1 is also connected via a resistor to VCC. So the math is a little more refined(as per datasheet), but basically that's it. Followed by a gain control stage, then a gated sample and hold before driving the meter.

[dbanner]

Then there was this which I found here on the forum. By Davor.



Based on some patent US4001602

[dbanner]

so isn't it just a ratio of 2 vector quantities. The angle subtended being the phase of the target, right. or something like that. Just in two quadrants for the purpose of demonstraing the basis.

[Altra]

I am sure Skippy can explain the math. Davor's analog divider sim is interesting. I'll bread board it and see if works the same as the simulation.

[dbanner]

here is the sim file

The patent explains the basis of this circuit with the 2 diodes. "Advantage is taken of the current-exponential voltage characteristic of a diode".