Back to the roots at 50: Introducing Spectral-G4 (AI meets VLF)

[Taktyk]

Hi everyone,

Some of you might remember me from years ago, others probably not - it’s been quite a while since I was active in the detector building community.

I’m turning 50 in just a few days, and as I hit this milestone, I found myself reflecting on the projects that gave me the most joy over the years. I’ve spent my professional career as an AI Engineer in the IT industry, dealing with abstract algorithms and data. But lately, I’ve been missing the "real" engineering - the smell of solder, the challenge of a low-noise analog front-end, and the magic of physics.

I always remembered the Geotech1 community warmly, as a place of true innovation. So, I decided to return to my hobby, but this time, I’m bringing my professional "AI toolbox" with me.

I’ve been working on a project I call Spectral-G4. It’s a VLF platform that represents my vision of how modern tech can revitalize our hobby. Instead of the usual phase-ID, I’m implementing Neural Spectral Fingerprinting.

A few technical teasers of what I’ve been up to:

18-bit SAR High-Speed Acquisition: Using the AD7690 to get a crystal-clear signal.
20-bit Effective Resolution: Implementing hardware dithering and oversampling (a bit of an obsession of mine).
Distributed Intelligence: A Dual-MCU architecture with a "Smart Probe" (STM32G0) doing active vector nulling inside the coil.
The AI Layer: Using TinyML on an STM32G4 to classify targets based on harmonic profiles.

I’ve reached a stage where M1 (Analog/Power) is completed, and I’m now diving deep into the DSP and AI layers. I’ve set up a technical showcase and a landing page to document the journey.

I’m doing this primarily for the love of the craft, though I am considering a small "Founder Series" for those who want to join the development.

It feels great to be back. I’d love to hear your thoughts on the architecture.

Technical Showcase: https://github.com/takzen/spectral-g4-showcase

Project Website: https://spectral-g4.pl

Cheers,
Christopher

[Taktyk]

Hi everyone,

As promised, I have developed a detailed 34-point roadmap for the Spectral-G4 project. It covers the entire journey from the first solder joint in the analog stage to the final neural network inference.
I’m breaking the project down into five logical phases to track the progress more effectively. Here is the full plan:

Spectral-G4: Detailed Project Roadmap

Phase 1: Analog & Power Core (The Foundation)

1. TX H-Bridge Design: Designing a full H-bridge power stage for 7.8 kHz square-wave transmission.
2. MOSFET Driver Optimization: Implementing high-speed gate drivers for ultra-sharp signal edges (rich harmonics for AI).
3. Power Harvesting Circuit: Rectifying and filtering the TX signal to wirelessly power the in-coil electronics.
4. Ultra-Low Noise LDO Setup: Cascade power regulation (e.g., LT3042) with >80dB noise rejection for the analog rail.
5. Preamp Stage (AFE): Designing the initial ADA4841-2 based low-noise gain stage with precision bandpass filtering.
6. Differential ADC Driver: Implementing the ADA4941-1 to convert single-ended signals to fully differential for the SAR ADC.
7. High-Precision VREF: 4.096V voltage reference (REF3240) with <5ppm/°C drift.
8. Dithering Hardware: Implementing analog linear dithering via 47p/120p precision capacitors.

Phase 2: Distributed Intelligence (Smart Probe)

9. Probe PCB Layout: Miniaturized, vibration-resistant PCB for the coil (STM32G0 + Toroid).
10. I2C Protocol Bridge: Binary communication protocol between the Base (G4) and the Probe (G0) via a 6-wire cable.
11. 12-bit Active Vector Nulling: Implementing vector-based digital nulling using dual DAC channels inside the coil.
12. Toroid Summation: Calibrating the Al1800 toroidal transformer (10t:37t) for perfect zero-offset balancing.
13. Thermal Drift Monitoring: Firmware-level temperature sensing for dynamic phase-balance correction.
14. Coil ID System: Storing coil parameters (Model/Batch/Calibration) in the G0 Flash memory.

Phase 3: DSP & Data Acquisition (The Brain)

15. SPI+DMA High-Speed Link: Configuring STM32G4 SPI for low-latency AD7690 (18-bit) data acquisition.
16. HRTIM TX Generation: Utilizing the High-Resolution Timer for nanosecond-precision Dead-Time control.
17. CORDIC I/Q Demodulation: Hardware-accelerated phase and amplitude extraction using the CORDIC unit.
18. 20-bit Oversampling Engine: Software decimation and dither filtering to push the 18-bit SAR to 20-bit effective resolution.
19. Harmonic Extraction: Simultaneous demodulation of the 1st, 3rd, and 5th harmonics (7.8kHz, 23.4kHz, 39kHz).
20. EMI Noise Cancellation: Automatic frequency scanning to select the cleanest operating point.
21. Ground Balance Algorithm: Vector-based subtraction with automatic ground tracking logic.

Phase 4: AI & Neural Classification (TinyML)

22. Data Logging Tool: Building a raw spectral vector capture tool (Dataset Collector) via USB-VCP.
23. Neural Signature Mapping: Collecting a comprehensive dataset for non-ferrous, ferrous, and "trash" targets.
24. Model Architecture Design: Designing a lightweight MLP neural network optimized for the Cortex-M4 core.
25. X-CUBE-AI Integration: Porting the trained model (TensorFlow Lite) to optimized C code for the STM32G4.
26. Real-time Inference: Implementing on-device classification in the main detection loop (<10ms latency).
27. Static ID Logic: AI-assisted target identification for the Non-Motion (Static) mode.

Phase 5: Software, UI & Mechanics

28. Antigravity Framework Integration: Adapting low-level drivers to the Antigravity C++ framework.
29. GUI IPS Rendering: Designing the graphical interface for the IPS color display (spectral visualization).
30. Polyphonic Audio Engine: Low-latency VCO audio controlled by real-time AI classification parameters.
31. Mechanical Design: 3D-designed housing and ergonomic carbon fiber shaft.
32. Field Benchmarking: Comparative testing against commercial flagship detectors in high-mineralization soils.
33. B2B GIS Integration: Implementing data logging (VDI + Coordinates) for archaeological mapping.
34. Final Assembly & Calibration: Final calibration procedure for the "Series 0" Founder units.

I will be updating the GitHub repository as I progress through these stages. Feel free to ask technical questions about any specific step!

[EL NINO]

I salute you, Taktyk, it definitely looks like a very interesting project.. I'm definitely interested in it..and I see potential in it..

The technical specifications and parameters of the project themselves look really good...and it will be interesting to see what AI can do when learning on various test fields... and then in detection in the field..

[Taktyk]

Hi everyone,

To give you a better "bird's-eye view" of the project, I’ve put together a high-level block diagram of the Spectral-G4 architecture. I believe that in modern VLF design, the way we handle the signal before it even reaches the MCU is what separates a standard detector from a high-performance instrument.

Here’s a breakdown of the signal flow and the logic behind my choices:

1. The TX Engine (The Excitation)
I’m using a full H-Bridge driven by the STM32G4’s HRTIM (High-Resolution Timer). While many modern designs move towards Sine waves, I’m intentionally using a 7.8 kHz square wave with ultra-sharp edges. Why? To ensure a rich harmonic content (3rd and 5th harmonics) which are essential for the Neural Spectral Fingerprinting later in the chain.

2. The Smart Probe (Distributed Intelligence)
This is the heart of the "active" part of the project. Inside the coil, an STM32G0 acts as a co-processor.

• Active Vector Nulling: Instead of relying solely on mechanical geometry, I’m using dual DAC channels and a precision toroid transformer to inject a compensation signal. This allows for dynamic, firmware-controlled balancing of the RX/TX offset.
• Power: The probe is powered via a harvesting circuit from the TX lines, reducing the need for extra power wires in the cable.

3. The Analog Front-End (AFE)
Low noise is my obsession here.

• Preamp: An ADA4841-2 handles the initial gain.
• Differential Conversion: I’m using an ADA4941-1 to drive the ADC. Converting to a fully differential signal at this stage is crucial for EMI rejection and to fully utilize the SAR ADC’s range.
• VREF: A stable 4.096V reference (REF3240) ensures that my 18-bit measurements remain consistent across temperature shifts.

4. Data Acquisition & DSP
The signal is digitized by the AD7690 (18-bit SAR ADC) via a high-speed SPI/DMA link.

• Dithering & Oversampling: By adding controlled analog noise (dithering) and oversampling in the G4, I’m aiming for a 20-bit effective resolution.
• Hardware Acceleration: The CORDIC unit in the STM32G4 handles the I/Q demodulation in real-time, leaving the CPU cycles free for the AI layer.

5. The Neural Layer (The Decision Maker)
The demodulated vectors (1st, 3rd, and 5th harmonics) are fed into a TinyML model (TensorFlow Lite for Microcontrollers). Instead of a simple VDI number, the system outputs a classification probability based on the target’s spectral "fingerprint."

I’m particularly curious about your thoughts on the Active Vector Nulling via the toroid. Has anyone here experimented with active digital compensation in the coil assembly?

[Taktyk]

Following my introductory post, I’m diving straight into the first module of the Spectral-G4: the Transmitter (TX) Driver Stage.

In most VLF designs, the TX stage is often overlooked, but for a project relying on Neural Spectral Fingerprinting, the quality and "sharpness" of the excitation signal are everything. If we want to analyze the 3rd and 5th harmonics, we need a TX bridge that can switch fast and clean.

The Schematic Breakdown:

1. Full H-Bridge Architecture: I’ve opted for a full-bridge topology using two Si4599DY complementary N+P channel MOSFET pairs. This allows for a 24V peak-to-peak swing from a single 12V rail, maximizing the magnetic moment without complex power rails.
2. High-Speed Gate Driving: To minimize switching losses and, more importantly, to achieve ultra-sharp square-wave edges, I’m using the TC4427COA dual MOSFET driver. It provides up to 1.5A of peak current to quickly charge/discharge the gate capacitances.
3. Current Monitoring (The Feedback Loop): You’ll notice a 0.1R 1W shunt resistor (R12) at the bottom of the bridge. The signal TX_CUR_TO_STM32 (after a simple RC filter) is fed back to the STM32G4. This allows the system to:
   • Monitor real-time power consumption.
   • Detect over-current conditions (shorted coils).
   • Potentially implement a software-based resonance tuning check.
4. Bulk Decoupling: I’ve placed a 220uF low-ESR electrolytic capacitor (C47) in parallel with a 1uF ceramic (C17) right at the bridge entry. Switching several hundred milliamps at 7.8 kHz can create significant ripples; keeping the TX noise isolated from the future RX stage is priority one.

Why Square Wave?
While sine waves are "cleaner" for traditional phase-ID, they are energetically expensive to produce and lack the harmonic richness I need. By using a precisely timed square wave (via the G4’s HRTIM with nanosecond dead-time control), I’m effectively "illuminating" the target with multiple frequencies simultaneously.

Technical Question for the experts:
I am currently debating the optimal value for the shunt filter (R13/C18). I want to capture the current envelope without introducing too much phase lag for the protection logic. What are your thoughts on current sensing in high-speed TX bridges for VLF?

I've attached the KiCad schematic of the TX section. Looking forward to your thoughts!

Cheers,

[Carl-NC]

What's the purpose of R13/C18?

At White's I did some work on dynamic coil nulling but not with a transformer. I could make it work decently for a sine wave but wideband was far more difficult.

[profesor]

What's the purpose of R13/C18?

At White's I did some work on dynamic coil nulling but not with a transformer. I could make it work decently for a sine wave but wideband was far more difficult.

Hi Carl. Do you have a more detailed explanation about dynamic coil reset?

I'd like to try it. Thanks.

[Taktyk]

What's the purpose of R13/C18?

At White's I did some work on dynamic coil nulling but not with a transformer. I could make it work decently for a sine wave but wideband was far more difficult.

Hi Carl,

You’re right to point that out. To be specific: R13 and C18 are strictly for TX coil current monitoring in the main unit.

The transformer-based nulling you’re referring to is actually located inside the coil assembly (what I call the "Smart Probe"). It’s a separate subsystem where an STM32G0 MCU manages the active vector compensation using a small toroid for signal injection.

To provide a bit more technical context on how this works:

1. Toroid Summation: I am using a high-permeability toroid (secondary winding in series with the RX coil) as a summing transformer. The compensation signal is injected directly into the RX path at the source, before it enters the cable.
2. Local Vector Generation: The STM32G0 generates a precise compensation vector. By having the "brain" inside the coil, I can minimize the phase shifts and EMI pickup that usually occur when sending low-level analog compensation signals through a long cable.
3. 8-Core Connectivity: To ensure maximum stability, I am using an 8-core shielded cable. This allows for dedicated power lines (VCC/GND) for the probe electronics and a separate digital bus for communication between the G4 and G0, keeping the RX signal as clean as possible.
4. The "Saturation Prevention" Strategy: Addressing your point about wideband difficulty. I am not aiming for a perfect wideband zero. The primary goal is to null the 7.8 kHz fundamental. By removing the "carrier" physically at the source, I prevent the RX preamp (ADA4841) from saturating. This leaves the full dynamic range of the 18-bit SAR ADC available to capture the 3rd and 5th harmonics, which the AI then uses for classification.

In essence, I'm using the hardware to handle the "brute force" (the fundamental) and the AI to handle the "nuance" (the harmonic residuals).

I've attached the schematic of the Smart Probe below. I’d love to hear your thoughts on this approach, especially regarding the stability of the toroid injection over temperature.

[Taktyk]

I noticed a small error in the schematic I just shared regarding the transformer (T1). On the secondary side (injection), there are actually 10x fewer turns compared to the primary. This step-down ratio is crucial for better resolution of the compensation signal and lower output impedance.

I should also mention that this specific part of the architecture is inspired by commercial coils from the Polish manufacturer Rutus. In their designs, they implement phase and amplitude balancing using an AD5242 digital potentiometer.

For the Spectral-G4, I’ve decided to evolve this concept:

• Instead of a digital pot, I am using the MCU’s DAC channels.
• This allows for much finer granularity and faster dynamic adjustments during the nulling loop, which is essential when trying to maintain a stable null in varying soil conditions.

I’ve attached the corrected Schematic v1.1 and a photo of the original Rutus coil internal board for reference, showing their implementation of the digital pot balancing.

[Carl-NC]

Hi Carl. Do you have a more detailed explanation about dynamic coil reset?

I tried several approaches. I'll roughly describe them but without much detail because I may consider one for a future product.

One way is to use a small series resistor to get the TX current waveform, dynamically scale this signal, and then apply it either to the preamp or to the RX coil directly. A limitation of this method is that it works for a sinusoidal TX but not for a square wave TX.

Another way is to use differential bucking coils and dynamically drive them based on an error signal. This works with any TX waveform.

Another yet is to use a differential coil system like this

and dynamically adjust the balance drive to minimize Vout.

[Geotech11]

How is it progressing?

[pito]

You can use BTL amp, however from my experience BTL is giving double coil voltage but draws 5 times more current compared to a single amplifier.

some of my testings

[Taktyk]

How is it progressing?

Thanks for asking! The project is progressing intensely. I’ve just finalized the complete schematics for the Spectral-G4.
All major blocks are ready: the high-efficiency H-bridge for multi-harmonic TX, the ultra-low-noise Analog Front-End (AFE), and the integration of the 18-bit SAR ADC with the STM32G4.
Now I’m moving into the most critical phase: PCB Design. With 18-bit resolution and AI processing, signal integrity and a low noise floor are everything. I’m focusing on a multi-layer stackup to ensure perfect separation between the high-current TX paths and the sensitive RX AI-driven processing