NEW !!! Full differential PI front end.

[nick_f]

Completed porting the detector code from the big expensive Spartan 3E board to the much smaller cheaper ( $US 49 ) Spartan 3e board.
cheerz from moodz.

Hi Paul,
I am very impressed with what you achieved with these Spartan boards. I checked on the internet where these boards can be purchased from and I could not find them, either on xilinx web site or from avnet. Could you please post a link where you bought them from?

Regards,
Nicolae

[moodz]

FPGA progress

Completed porting the detector code from the big expensive Spartan 3E board to the much smaller cheaper ( $US 49 ) Spartan 3e board.

The design fits very nicely into the chip and the four channel scope and VGA display function is still included.
LCD 2 x 16 char driver OK.
Rotary encoder control for volume etc OK
Pulse Generator for PI Tx OK
DSP processing chain OK
2 x 24 bit ADC input OK
Serial Port at 115.2 Kbit OK
32 Bit CPU @ 50 MHz OK


I have ordered the Mosfet driver chips to interface to the 3.3 volt cmos ports on the fpga and the 2 x 16 LCD displays and Rotary switches.

Below you can see that the board is quite compact. There is 24 bit ADC chip plugged into one of the IO ports for testing. There is a 40 pin header to connect to the front end board. The frontend board will carry the Mosfet, protection diodes, Amp ( if required ), ADC, damping resistor etc ... not much really.

The total cost of all the electronics and case will be cheaper than $US 100
Add your poles and coils of choice.



Success ! the MooDz detector runtime starts up on the small board.



cheerz from moodz.

[moodz]

FPGA progress

..more coding progress.
Vertical channels adjustments now available to CPU.
Added LCD driver HDL.
Added Rotary knob driver HDL.
The LCD display is accessed via the VGA RAM. By writing to specific 32 characters addresses in video ram the LCD is written also. This is helpful for menu displays when the VGA is not connected to the FPGA board.

The development board is a Spartan 3E500 from digilentinc.com

here are the 4 channels displayed 600 x 800 from the VGA port on the FPGA board showing raw input from the on board ADCs



below .. the board showing the LCD ... note the text in the lower right hand corner of the VGA in the pic two up. The LCD displays on the VGA as well.



below is the serial console attached to RS322 port 1 on the Spartan board. 115.2 Kb
If you want to read / write stuff from memory the addressing is 32 bits The video ram starts at 0x50000000 Line 1 of the LCD is at 0x50001040. You can read and write memory from the console menu. The rotary knob is available on the IP port GPIO bits 0 to 7. The 8 LEDs on the board will also change according to the Knob being turned.



If you want see the moodz detector platform for real I have supplied the bitfield file ... you will need the Xilinx Impact tool to load it into the board ( you will have to supply the board ).
dspexplorer.bit.zip

TODO ... put the DSP filters back in and the pulse generator. What I am working towards is a general purpose but high performance platform for testing different MD technologies. With the right ADCs and DACs this puppy will also do VLF / IB as well as PI. All the controls for the TX, Rx, displays, filters, knobs, switches, DACs and ADCs will be available as GPIO or memory mapped to the CPU. The CPU really only has to do some housekeeping ( user menus and mode switching etc ). The CPU is MIPs compatible and has an update GCC toolchain which can generate highly optimised code.

MooDz

[moodz]

Here they are ...

Hi Paul (moodz),
What ever happened to the work you were doing on the zpi 1.0 with the dspic controller?
Did you ever publish the dspic code? From the forums, it looks like you got lured away by the fpga project. I would like to have a go at the ZPI design as I am not up to speed on fpgas, but have worked quite a bit with the dspic. The zpi design was a nice combination of hardware and software. The complexity is appropriate for the home brewer to make PCB's and software modifications. Would you consider sharing the dspic code?
cheers from Canada

Note this code is by no means complete ... it was mainly built to test the differential front end.
Here are the last few builds... the last couple of builds up to 18 are missing for some reason however most of the guts is there. There are main modules to do the fast ADC, RS232 comms to dump waveform, integration and even FFT. What is missing is LCD driver, menu,rotary knob controls and ground balance subtraction. Hopefully you can read the code and figure something out. Note that the TX pulse is really rudimentary ... I was going to setup a PWM output ... never got round to it. The ADC starts sampling the waveform straight after the Tx pulse as I remember it. Stuff comes out the RS232 ports to monitor what is going on.

Have fun. Moodz.

Metal10.zipMetal11.zipMetal13.zipMetal14.zip

[ve7it]

Hi Paul (moodz),
What ever happened to the work you were doing on the zpi 1.0 with the dspic controller?
Did you ever publish the dspic code? From the forums, it looks like you got lured away by the fpga project. I would like to have a go at the ZPI design as I am not up to speed on fpgas, but have worked quite a bit with the dspic. The zpi design was a nice combination of hardware and software. The complexity is appropriate for the home brewer to make PCB's and software modifications. Would you consider sharing the dspic code?
cheers from Canada

[moodz]

Hey Moodz,

Is that the $49 Xilinx starter kit from AVNET? I've almost purchased one several times now, but haven't done so as of yet. I keep wondering how much time I'll have to work with it, given all of my other projects that are in the works right now. (None of these current projects are MD related, unfortunately.)

It sure is ... since I had to pay $US 70 in postage I bought six of them.

[Krzysztof]

Hey Hobbes Lives.
I think. it it that was one should was several months; this oneself it tells easily but new family, technology plus instruments. It was one should work in addition details - this lasts.
I wish pleasant adventure it - goes new!
I begin just recognizing technology PSoc Cypress, so as FPGA but from additional analog blocks and memory FLASCH as well as core M8 or Cortex to choice: 8, 16, 32 bit. All in one ankle - until it turns me with curiosity, I got already today set and programmer unit.
I want to alter from Atmel my MAG on new family PSoC, I start just!
Best regards Chris.

[hobbes_lives]

Hey Moodz,

Is that the $49 Xilinx starter kit from AVNET? I've almost purchased one several times now, but haven't done so as of yet. I keep wondering how much time I'll have to work with it, given all of my other projects that are in the works right now. (None of these current projects are MD related, unfortunately.)

[WM6]

Shortly I will post a block diagram of the system as I know some of you are having trouble following what we are talking about.

moodz

Very nice aim, moodz. Thanks in advance.

[WM6]

What about a high efficiency, high sensitivity detector, with only essentials, to keep cost down?

Hi Tinkerer

From my perspective, that's goals are exactly what you wrote here.

I think this applies to anyone who uses detector to find something and not to the bells and whistles parade.

Best wishes

[moodz]

The min power is very hard to peg ... for instance the big board draws about 220 ma at 5v which is just over 1 watt. The smaller board draws half that. However you have to consider that the power consumed by an FPGA is related to the complexity and how fast the clocks are. Similiar to a CPU the more you work it the more power it consumes. You can however design to turn off clocks in unused parts etc. Because this design is a PI I would expect energising the coil to consume the bulk of the power.
There are next generation FPGAs around that will draw much less than these chips used here.

moodz.

[simonbaker]

I need to retire so I can get my head around this stuff. It's good.

What do you think the min power required ultimately would be for a detector based on these boards?

Regards,

-SB

[moodz]

FPGA update

the FPGA project has split across two boards now ...
The new board is much smaller .. sucks less power ... but will still have the same horsepower in the DSP department ..

The larger green board is the current development system. The smaller red board is the new development system split. This board is $US 50 which is a 1/3 of the cost of the larger board. It will still have the VGA waveform output capability.

Shortly I will post a block diagram of the system as I know some of you are having trouble following what we are talking about.

moodz

[moodz]

Hi Mootz,

I don't follow what you mean here...



I was reviewing the datasheet for the WM8786, and it looks like it can only be configured for a maximum sample rate of 192kHz. In master mode, the oversampling ratio can be set to 128fs or 256fs. If you don't mind, can you please explain in more detail how you have the WM8786 configured?

Thanks.

Hi Hobbes .... a long time ago I read an article how you could overclock microprocessors by tuning up the voltages and the input clock ( we are talking Z80s here so more than 20 years ago ) I have overclocked every computer I have ever had since then ....

To cut a long story short I dont particularly pay too much attention to data sheets ... you can clock the chip at whatever will work.. This chips specs the maximum master clock at 40 Mhz however to adhere to digital audio standards you must use the specific clocks ... but hey ... I am not doing audio here so I use whatever does it for me. This particular chip will clock all the way up to nearly 50 megs but starts to miss a few conversions ... this is equivalent to approx 380 Ksps

I was clocking at a higher frequency because I had not bothered to code the FPGA clock for the required clock ... so I just used the nearest.

However I am now using the correct clock ... as I realised there is no need for overclocking.
The input clock is set now to 24.576 Mhz for oversample of 128fs where fs is the desired sample rate of 192 Khz.
So 128 x 192000 = 24576000 ... ie 24.576 Mhz

However 192 Khz is plenty fast for this application this equates to a time BETWEEN samples of 5.208 us .... The sample and hold window is much faster than this ... so we only need to slide the phase of the ADC clock to sample at precise points on the RX waveform. The sample window is well under 1 us ... it is the conversion time that takes up the rest of the time till the next window.

This means we can use these cheap chips in place of much more expensive and faster ADCs because we are controlling the point at which a sample is initiated by controlling the phase of the clocks ...

Moodz.

[hobbes_lives]

Hi Mootz,

I don't follow what you mean here...

I clock them at a 200x oversample for an effective external sample at 200 Khz = 5 us

I was reviewing the datasheet for the WM8786, and it looks like it can only be configured for a maximum sample rate of 192kHz. In master mode, the oversampling ratio can be set to 128fs or 256fs. If you don't mind, can you please explain in more detail how you have the WM8786 configured?

Thanks.