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Rest assured that the PCB as defined with the gerbers that I posted works just fine as I have already built two of the units which both function correctly.
I had the PCB's manufactured by 'PCBWay' in China and they had no issue with the manufacture either.
I also checked the Schematic in V6 and it does report some errors, specifically to do with power connections. These are actually connected on the PCB, I suspect that they might have changed the way power definitions are defined and used from V5 to V6.
The files are supposed to be upwardly compatible, but there were some major changes to the schematic and symbol formats. Apparently they've now moved to using S-expressions notation, so maybe that's the problem.
I uploaded my Gerber files to JLCPCB ... and less than 2 minutes later they're were reported as in production!
Thanks for the feedback, I too have used many different professional EDA packages over the years and am very impressed at what KiCad has become (Especially the price).
I originally designed the schematic and PCB using KiCad version 5 and that is what I used to generate the Gerbers.
In version 5 the schematic ERC and DRC on the PCB side was totally clean (Except for courtyard clearances which I set to ignore).
I suspect that my routing rules didn't fully translate to version 6 as I've just done a DRC using V6 and as you say it seems unhappy with a lot of things.
I didn't supply the project file as it references some files and libraries which are custom on my Mac, when I get the time I'll try to clean it all up in version 6 then publish the updated project etc.
Rest assured that the PCB as defined with the gerbers that I posted works just fine as I have already built two of the units which both function correctly.
I had the PCB's manufactured by 'PCBWay' in China and they had no issue with the manufacture either.
I also checked the Schematic in V6 and it does report some errors, specifically to do with power connections. These are actually connected on the PCB, I suspect that they might have changed the way power definitions are defined and used from V5 to V6.
I just wanted to say "Thank You" for re-sparking my interest in KiCad. I've been using DipTrace, and recently upgraded to the 500 pin version. However, a design I'm working on has 582 pins, and I didn't want to pay the extra money to upgrade to 1000 pins.
When I last investigated KiCad it was a bit weird and clunky in the way it worked, and I did not get a very good impression of the software having used several other commercial PCB packages. Now with Version 6.0, things have changed dramatically. I really like the PCB interactive router, and the way that the general usage has become much more intuitive. It more or less works as you would expect it to. The only thing missing is the ability to renumber the reference designators in the PCB and backannotate to the schematic. However, that's not a show stopper. Someone has written a Python plugin that apparently adds this feature, but I haven't tried that yet. KiCad also has the advantage that it runs in native Linux, unlike DipTrace which requires the use of Wine. This makes it run faster and more smoothly than DipTrace.
Anyway, the design is complete, and passes all ERC and DRC checks, and Gerber files are ready to go to JLCPCB.
For anyone interested in looking at KiCad 6.0, then go here ->
By the way, I also took a look at your Beachmaster design in KiCad. As you didn't supply the project file, there are some things that cannot be accessed.
I ran an ERC check in the schematic editor and it reports 4 errors and 18 warnings, and DRC in the PCB editor reports 67 errors and 74 warnings.
Some of the errors in the PCB may cause you problems. If you get stuck eliminating some of them, I should be able to assist if you can supply the complete project. It was also not possible to run a schematic / PCB parity check due to the missing project file.
Nice looking boards, what are the other larger boards with the rounded cutouts?
When assembling the Beachmaster boards, remember to use the Fab files for component location as the silkscreen ID locations get a bit cramped in places.
Post #24 above has the latest doc pack which includes all files including the 'Fab' files and updated 'Build' document.
Good luck with the build and let me know how you get on.
for sure it will work as intended. The resistor R8 also limits the TX current. In your circuit, the current has the possibility to bypass the R8 throughout the transistor.
In my TX circuits, I draw it always as seen in the previous uploaded image.
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