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PICKINI V4 - an easy to build, self adjusting PI detector

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  • SaltyDog
    replied
    Originally posted by waltr View Post
    Yes, sounds good.How are you measuring the 'slope'?
    What gain are you running on the pre-amp? Did you drop gain to 7 as you posted above?
    Would like to see timing of sampling and flow chart of processing.

    What is you ferrous target? How you tried a rusty nail are different angles?
    HI, I am measuring the slope by taking multiple slices early in the discharge curve (I can take as many as I like with the FPGA as it's only a line of code .. )

    Running standard gain at the moment (>1000) as I am using stock MPP board. When Pickini board arrives, I will play around with the gain as well as the offset level ..
    (The offset level I will drive via an DAC which will be the output of a PID control loop ..to keep it steady ..)

    I will adjust the offset to make sure my ADC window is in the area of interest on the slope, so I will sample early for discrimination, then late in the slope for sensitivity ..

    Yes, rusty nail works at any angle ... I can't do any in-depth testing till I get the hardware .. I will do the best I can with my current set-up.

    PS: I also have a custom micro-controller in the FPGA that links all the hardware together and spits out data via a USB port ...

    Leave a comment:


  • SaltyDog
    replied
    Originally posted by F117 View Post
    Just to be clear:
    The opamp offset is controlled by the PIC DAC output which has only 5 bits of resolution. This calibrates the DC steady state level to about 4V at the input of the internal comparator.
    The comparator slice level ( the other input of the internal analog comparator) is controlled by a 10bit PWM output.

    Hi Bernard,

    You misunderstand ... currently my FPGA stuff is running with with an MPP board, I am just using it's front-end op-amp.
    I am using that board to try this stuff on, since your board has not arrived due to COVID-19.

    Your resolutions have nothing to do with what I am implementing in an FPGA ..

    What I have achieved is discrimination because I have looked at the early part of the slope ... discrimination info is lost once you slice at the tail end of the slope .

    My intention is to do "both" early slice for discrimination and late slice for sensitivity .. hope that makes sense ..

    Leave a comment:


  • waltr
    replied
    Originally posted by SaltyDog View Post
    Ok, I have had some success with this, I can now discriminate between gold and ferrous, with code running on my FPGA.

    I have used a MPP board to provide the front end, I have connected my fpga to the op-amp output, via an A.D.C. And I am looking at the slope just after the op-amp comes out of saturation...

    Ferrous materials give a decrease in slope, and gold gives a slight increase, I have still some work to make it more sensitive, but as it stands, does discriminate well..

    I have 9 bits of resolution to the slope at present..

    When I get the Pickini board, I will finish the design..
    Yes, sounds good.How are you measuring the 'slope'?
    What gain are you running on the pre-amp? Did you drop gain to 7 as you posted above?
    Would like to see timing of sampling and flow chart of processing.

    What is you ferrous target? How you tried a rusty nail are different angles?

    Leave a comment:


  • BC547
    replied
    I won't be able to get it more sensitive to discrimination until I can accurately control the op-amp offset, hence the need to wait for the Pickini..
    Just to be clear:
    The opamp offset is controlled by the PIC DAC output which has only 5 bits of resolution. This calibrates the DC steady state level to about 4V at the input of the internal comparator.
    The comparator slice level ( the other input of the internal analog comparator) is controlled by a 10bit PWM output.

    Leave a comment:


  • SaltyDog
    replied
    Originally posted by 6666 View Post
    Sounds good
    Thanks...

    Just to be clear, I have 9 bits resolution for the analog side, 12 bits measuring time over the slope..
    I won't be able to get it more sensitive to discrimination until I can accurately control the op-amp offset, hence the need to wait for the Pickini..

    Leave a comment:


  • 6666
    replied
    Originally posted by SaltyDog View Post
    Ok, I have had some success with this, I can now discriminate between gold and ferrous, with code running on my FPGA.

    I have used a MPP board to provide the front end, I have connected my fpga to the op-amp output, via an A.D.C. And I am looking at the slope just after the op-amp comes out of saturation...

    Ferrous materials give a decrease in slope, and gold gives a slight increase, I have still some work to make it more sensitive, but as it stands, does discriminate well..

    I have 9 bits of resolution to the slope at present..

    When I get the Pickini board, I will finish the design..

    Sounds good

    Leave a comment:


  • SaltyDog
    replied
    Ok, I have had some success with this, I can now discriminate between gold and ferrous, with code running on my FPGA.

    I have used a MPP board to provide the front end, I have connected my fpga to the op-amp output, via an A.D.C. And I am looking at the slope just after the op-amp comes out of saturation...

    Ferrous materials give a decrease in slope, and gold gives a slight increase, I have still some work to make it more sensitive, but as it stands, does discriminate well..

    I have 9 bits of resolution to the slope at present..

    When I get the Pickini board, I will finish the design..

    Leave a comment:


  • SaltyDog
    replied
    Originally posted by F117 View Post
    Only the part of the flyback pulse where it returns to steady state is interesting.
    I agree the part close to the steady state is interesting for "sensitivity", but I think the earlier part of the pulse, once it get's below the diode voltage, is more useful for detecting the type of metal (see graph again) ..
    I intend to look at that part as well with a different slice level .... that way we get the best of both worlds ... sensitivity to small targets, and discrimination ..

    So once your kit arrives (.....dang Covid-19) I am going to work on that part with my FPGA code ..

    Cheers

    Leave a comment:


  • BC547
    replied
    So, it's more about resolution in measuring pulse width
    Correct. That is why we want to measure the pulse width as close to the steady state voltage as possible.
    If you slice the pulse too close to steady state, the results will become unstable.

    Only the part of the flyback pulse where it returns to steady state is interesting.
    That is why both offset and gain of the opamp are optimized to output only that small portion of the flyback pulse.
    The further you slice the pulse from steady state, the less sensitive it will be.

    Leave a comment:


  • waltr
    replied
    Originally posted by SaltyDog View Post
    Right, but since this is a"temporal" application, we are looking for sensitivity in the time domain, not voltage ... So, it's more about resolution in measuring pulse width..
    Give it a try and post results.

    Leave a comment:


  • SaltyDog
    replied
    Right, but since this is a"temporal" application, we are looking for sensitivity in the time domain, not voltage ... So, it's more about resolution in measuring pulse width..

    Leave a comment:


  • waltr
    replied
    Originally posted by SaltyDog View Post

    1. Can you explain why the op-amp gain needs to be >1000 when the input voltage range is 0..0.7v and the output range is 0..5v
    Seems to me only a gain of 7 is required ... is there something I am missing?
    Since most desired targets are small and the returned target signal is very small only to lowest few uV of the decay curve has target information.
    Therefore, a gain of ~1000 is needed to get the few uV up to a few mV.

    If you build and measure then it will become clear.

    Leave a comment:


  • 6666
    replied
    Originally posted by SaltyDog View Post
    Hi, I built a spider weave coil that is constructed from copper wire (0.5mm) which is cotton covered by 1mm cotton. It is the cotton wire in combo with the spider
    weave that gives very low capacitance. (I have had a lot of experience building there for high voltage/current Telsa coil applications)

    The coil is 160uH and 1.6E ...
    [ATTACH]49751[/ATTACH]

    Thanks we used to use it here in Australia back in the 1960-70's , have not seen it for long time.

    Leave a comment:


  • SaltyDog
    replied
    Hey Bernard,

    Glad to see forum is back up .... I have a couple of questions for you.

    1. Can you explain why the op-amp gain needs to be >1000 when the input voltage range is 0..0.7v and the output range is 0..5v
    Seems to me only a gain of 7 is required ... is there something I am missing?

    2. Could you please explain the function of the op-amp offset and calibration function, and why it is essential ..

    Many Thanks,

    PS: I am thinking of implementing your design hardware completely in an FPGA .... I already have the FPGA tracking a 2..5us slope, and reporting the result ..

    Leave a comment:


  • SaltyDog
    replied
    Originally posted by nickel_n View Post
    do you have a link to a supplier?

    Sorry .. It is a bobbin of wire I have had for some time .... I have no idea when and where I got it ..
    I suspect I got it when I was working, but now I have been made redundant, no longer have access to corporate emails ..

    However, if you look for cotton covered copper wire of the dimensions I mentioned you should be all good .. you do need at least 1mm thick cotton ..

    Leave a comment:

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