New Bipolar Boost TX and Front End

[Mdtoday]

Nice work JL.
Yes, the AXI interface is a beast, I had to write some test code for an ECU some time back and it did my head in for a while.
I started off with Xilinx examples and found they had bugs, so still had to figure it out, which I eventually did but after reading the article you linked to, I wish I had that at the time, sure would have helped. Well written, thanks for the link.

The changes made to your code is looking very good, and the audio is going to be great, nice work.

Ill run the simulator tonight when I get home, been very busy with work.

The connectors should be delivered in a day or two so I'll be able to finish 2 sets of boards off.

Again, thanks for sharing.

Cheers

Mdtoday

[KingJL]

Added AXI4 communications interface & defined an audio module

This weekend I added an interface to the AIX4 bus that will be needed when we package the TX-RX as a peripheral for use with the MicroBlaze embedded processor. The AIX4 bus interface is is thoroughly confusing and the Xilinx ip for using the interconnect provides little if any insight... Then I run across a blog article by Dan Gisselquist, Ph.D., Gisselquist Technology, LLC. So much easier to understand... and whats more he provides a module that interfaces the full AXI4 protocol to a simpler register based interface. Originally, I had designed the register based interface to have one channel for both read and write with separate enable signals. To interface with the AXI4 bus and the microblaze embedded processor requires separate channels for read and write, so I changed the register interface to provide that functionality. Also the AIX4 bus interface provides a reset signal that is low when active, so I changed all reset processing to work with a active low.

The latest Vivado_Bipolar_TX(7-1-2019).zip containing the project files can be found here.

I also defined an audio module for use with the project when we get to the stage where it is needed. The audio module consists of a numerically controlled oscillator (NCO) with a sine lookup table that passes a 10 bit sinusoidal signal to a pulse density modulation (PDM) encoder. I have designed the audio module to provide a sinusoidal tone that is between 190Hz and 3050Hz controlled by a frequency control word that is normally the value of the processed target signal. The frequency out (F) is F = CLK * FCW / (2**accumulator size (bits)). As designed the CLK = 100MHz and accumulator size = 29 bits. To keep the oscillator frequency within design limits, any time the input FCW is greater than 2^14 we subtract 2^12 ... any time the FCW is less than 2^10 we add 2^12. Sounds strange but it works. The DPM is clocked at 100 MHz also so the output can easily function as a 1 bit dac by filtering with a low pass RC filter with a cutoff of ~ 3000Hz.

The Vivado simulator waveforms for the audio module (FCW = 4096):

The Vivado project for the audio is in the ./Audio subdirectory (off of the Bipolar_TX directory) contained in the project zip.

[KingJL]

... I ended up purchasing a lot of passive components from LCSC this time around just to try them out...

Thanks for the tip... just checked them out... cut my Mouser order down to just 5 items (THAT1512, DG418B, OPA828,FDS4935BZ,FQS4901).

[Mdtoday]

Well, all the company has gone back to their respective homes... so now back to the project!

First a recommendation/observation... R1 and R2 are the wrong value for safe operation of the inrush current limiter.
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I am putting Ebay and MOUSER orders together to exercise after the 1rst of July for the parts that I do not already have. So I should be populating the PCB's in parallel with working on the hardware definition. Soon it will be time to bring the MicroBlaze embedded CPU into play.

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Thanks for the info JL, I will make and test those changes in next day or so.
I have 99% of components now, just the interface connector to be received, I ended up purchasing a lot of passive components from LCSC this time around just to try them out. parts were here in 4 days. I added a few reels of commonly used values of R & C components I use. At prices of around $5-$8 per 4000 , for Yageo brand, I couldn't resist.

The sampling section described is looking really good, thanks for sharing, I will download and have a look at the latest files.
The proposed audio generation method is a nice slick way of implementing the sound output, I like it.
I think the embedded MicroBlaze CPU will have an easy time.

Again thanks for sharing your project, I'll post up some progress photos of PCB assembly soon.

Cheers

Mdtoday

[KingJL]

Updated Vivado Design Files

Well, all the company has gone back to their respective homes... so now back to the project!

First a recommendation/observation... R1 and R2 are the wrong value for safe operation of the inrush current limiter. Using R1 and R2 at the stated value (1 ohm) would result in a maximum input current of 2.5A... substantially above the 1.5A spec for the LM317. I would recommend that only R1 be utilized (leaving R2 position unpopulated)... this will still permit an input current of 1.25A. Using 1.5 ohm for R1 and R2 would result in an input current of 1.666A... slightly over the 1.5A spec.

I have added to the FPGA hardware definition. Added the S0 filter and added logic so that the S0 output can tune the damp start time. Also added a Finite State Machine (FSM) to control the events immediately after turn on or immediately after a timing change. Now the sequence is (1) calculate all event timings and filter decimation rates, (2) fine tune the damp start time, (3) determine the static coil decay value for samples 1,2, & 3, (4) determine the ground + coil decay for those same samples, (5) normal operation. The ground and coil decay samples will be used to normalize the S1, S2, and S3 samples so that we are essentially dealing with target strength at these sample times. Left to implement are the finishing target FIR filter and the (very) slow ground/mineralization filter. The slow ground/mineraliation filter will further modify the main S1 and S2 target data that is fed to the finishing FIR filter. The output of the FIR finishing filter will be passed (via the I/O register set) for use by the embedded processor. All of the intermediate stage target data is presented via the I/O register set so that future processing decisions can be made without changing the hardware definition.

I plan on using the Digilent rotary encoder pmod to facilitate user input to facilitate user input to change operating modes/parameters. I have also been researching the method to provide an audio output. I think I have decided to use the Vivado DDS ip feeding a PWM (or a pseudo PDM) to implement a 1 bit DAC. The DDS will be driven by the target value after reaching a predetermined threshold.

I am putting Ebay and MOUSER orders together to exercise after the 1rst of July for the parts that I do not already have. So I should be populating the PCB's in parallel with working on the hardware definition. Soon it will be time to bring the MicroBlaze embedded CPU into play.

The new Vivado_Bipolar_TX(6-27-2019).zip containing the Vivado project can be found here.

[Mdtoday]

The restructured VHDL is much more organized and easier to read and comprehend (at least in my opinion).

You'll notice that the RX CIC filter starts showing the effects of input data at about 800 usec and keeps increasing until it reaches maximum value at about 20.5ms. The presence of output data is observed by the appearance of the "RX_DATA_RDY_o" signal. The value of the RX data for all three samples is in the last 3 entries of the "register_set" array.

Nicely done JL, very clean, great job and a lot of work, thanks for sharing.

The filtering looks really good.

Cheers

Mdtoday

[KingJL]

Major VHDL Restructure

I have radically restructured the VHDL code. It now consists of 3 (later to be 5) modules, TX_RX, TX_Timing, and RX. The top module TX_RX manages the communications register, calculates the clock counts for PRT, PW, TX_Boost, DAMP, RX_blanking, etc for the TX_timing module and CIC decimation rate for the RX CIC filter. It also receives the RX data from the RX module, posts it in the communications register, and notifies the host that new RX data is available. The restructured VHDL is much more organized and easier to read and comprehend (at least in my opinion).

The link to the new zip ( Vivado_Bipolar_TX(6-17-2019).zip ).

A sim run of the restructured VHDL:

You'll notice that the RX CIC filter starts showing the effects of input data at about 800 usec and keeps increasing until it reaches maximum value at about 20.5ms. The presence of output data is observed by the appearance of the "RX_DATA_RDY_o" signal. The value of the RX data for all three samples is in the last 3 entries of the "register_set" array.

[Mdtoday]

I guess so!!!!


A million "I thank you"s!'

Almost done with restructuring of the VHDL. Have everything working... VHDL much less cluttered. The output of the CIC filter actually starts to appear after ~8 ms. It really shows up when running the simulator with the restructured code which show when RX data is available from the RX module. Will be posting the update later this evening.

Great to see they arrived ok and you are very welcome, thanks for sharing your project.

Excellent news on the VHDL, its sounding very promising.

Went to order the power mosfet STB8NM60T4 last night and realised the package type is the larger D2PAK.
I have ordered STB5NM60T4 which is the DPAK

Oh and I short changed you on the boards, I have an extra 2 sets here I pulled out of the pack to have a look at under the scope but they didn't make it back in the bundle lol, oops!

cheers

Mdtoday

[KingJL]

... You should see a delivery very soon...

I guess so!!!!






A million "I thank you"s!'

Almost done with restructuring of the VHDL. Have everything working... VHDL much less cluttered. The output of the CIC filter actually starts to appear after ~8 ms. It really shows up when running the simulator with the restructured code which show when RX data is available from the RX module. Will be posting the update later this evening.

[Mdtoday]

I plan on using these (I have 5 of them) for my 20V and 5V power supplies. I included inrush protection on the board to prevent a current higher than they will tolerate.

It will be at least a week before I start populating the boards, as I have family coming to visit next week. I am also going to do some major restructuring of the VHDL. The TX_Timing module is becoming too large and unwieldy to be able to easily comprehend the logic. I am going to break it up into 4 or five modules, namely TX_RX, TX_Timing, RX, Compensation_Feedback, and CIC_Comp_Filter. That will make the logic contained in all modules less complex and should make everything easier to comprehend.

A word of caution as you test. A slip of a probe off a pin of an SMD device can easily destroy your FPGA. I have over 50 yrs experience working with electronics circuitry and yet I recently destroyed a VMH3CS logic board and had to have it replaced. A probe slipped off a pin of a 16 pin SOIC analog switch and ended up taking out an FPGA output pin that resulted in shorting out the 3.3V supply.

I will be using this board I designed some time ago, its good from 4-36v @ 4A protected, I have quite a few of them built , so will make up a rig for testing using a couple of them.

The modular restructuring sounds good.

I've been in the electronics game for over 40 years, had my share of smoke n sparks and I'll heed your words of caution, hats off to you for your over 50 years JL, that's a lot of experience and it shows.

You should see a delivery very soon.

Cheers

Mdtoday

[KingJL]

... I am about to start loading 2 sets of boards, I'll need to order the inter-board connector and I'm stilling waiting on the inductors to be delivered and jig up a 20v supply, so hopefully I can start checking power supply stages in a day or so at least...

I plan on using these (I have 5 of them) for my 20V and 5V power supplies. I included inrush protection on the board to prevent a current higher than they will tolerate.

It will be at least a week before I start populating the boards, as I have family coming to visit next week. I am also going to do some major restructuring of the VHDL. The TX_Timing module is becoming too large and unwieldy to be able to easily comprehend the logic. I am going to break it up into 4 or five modules, namely TX_RX, TX_Timing, RX, Compensation_Feedback, and CIC_Comp_Filter. That will make the logic contained in all modules less complex and should make everything easier to comprehend.

A word of caution as you test. A slip of a probe off a pin of an SMD device can easily destroy your FPGA. I have over 50 yrs experience working with electronics circuitry and yet I recently destroyed a VMH3CS logic board and had to have it replaced. A probe slipped off a pin of a 16 pin SOIC analog switch and ended up taking out an FPGA output pin that resulted in shorting out the 3.3V supply.

[Mdtoday]

The simulation ran fine KingJL, nice work and thanks for sharing



cheers

Mdtoday

[Mdtoday]

New update for the Vivado project...

New link for zip ( Vivado_Bipolar_TX(6-15-2019.zip ) containing the updated project:
https://drive.google.com/file/d/1ZMR...ew?usp=sharing

Thank you JL, I will try this tonight, It's looking very good.

I am about to start loading 2 sets of boards, I'll need to order the inter-board connector and I'm stilling waiting on the inductors to be delivered and jig up a 20v supply, so hopefully I can start checking power supply stages in a day or so at least.


Cheers

Mdtoday

[KingJL]

Added 3 channel CIC sample integrator filter

New update for the Vivado project... Corrected a logic error that prevented sample 0 (2 usec after start of damp for purposes of tuning the damp timing) from ever being taken. Added the 4 stage, 3 channel CIC filter that filters samples 1, 2, & 3 and integrates the sample output from the XADC. I initially configured the CIC filter to operate in streaming mode with no success. I reconfigured the CIC to not use the streaming option (operates in block mode) and successfully instantiated the CIC sample filter. Added logic to read the samples as they are made available from the CIC and store them in the interface register set.

To run the Vivado simulator to exercise the module logic (after you have created a project folder for the project and unzipped the project file into that folder). Start Vivado, open the project and in the "Hierarchy" panel, expand "Simulation Sources"; right click "sim_1", select "RUN Simulation">"Run Behavior Simulation". After the simulation starts, in the Menu Bar, select "Run">"Restart". Then in the "Objects" panel, right click "CLK100_i", and select "Force Clock". In the "Force Clock" dialog box enter 0 into "Leading edge value:", enter 1 into "Trailing edge value:", enter 10ns into "Period:", and click "OK". Then in the Menu Bar select "Run">"Run for". In the "Run for" dialog enter the time that you wish to run. For viewing the timing signals, I usually run for 10 ms. To see the outputs for the CIC filter you need to run for more than 30 ms... I usually run for 50 ms as it allows for the filter to reach maximum output. After the "run for" time is reached (or while it is running) in the Logic Waveform panel Menu Bar click the "Go to Time 0" symbol, and the repeatedly click the "Zoom out" symbol until you have the time span that you want to see.

New link for zip ( Vivado_Bipolar_TX(6-15-2019.zip ) containing the updated project:

https://drive.google.com/file/d/1ZMRfJohStrGblksMKnom00V4avBzz-Da/view?usp=sharing

[Mdtoday]

I have restructured the I/O interface for control of the TX by the embedded CPU. All control I/O with the module is now via a register array (currently 6 x 32 bit registers). The initial operating parameters are set by a set of generic's for the entity definition. This will allow the timing functions to be exercised without the inclusion of the embedded cpu or with minimal code for the embedded cpu.

Also the constraints file (CMOD-A7_master.xdc) has been modified to connect the output ports to the TX_IF_CMOD-A7 board J1.

The link to the new zip (Vivado_Bipolar_TX(6-13-2019).zip) file containing the Vivado project files is:
https://drive.google.com/file/d/1gEa...ew?usp=sharing

Very nice work KingJL thanks for sharing