Hi Detectorist#1 and @GeoMac,
I cannot thank you both enough for taking the time to review my schematic. As a learner, getting guidance from experts like you is a huge privilege, and your practical insights are literally saving this project!
Detectorist#1:
I have carefully followed your instructions and updated the design:
1. Power Supply: Removed C1 to C8. Kept only C9 (4700uF/35V Low ESR) and added a 100nF/50V ceramic capacitor in parallel.
2. L1 Inductor: Replaced L1 with a 1 Ohm (0.5W) resistor.
3. MOSFET: Swapped the Drain and Source connections so they are now correctly routed.
4. Damping Resistor (R
: Replaced the single 330-ohm resistor with three 110-ohm (3W) resistors connected in series to handle the flyback voltage safely.
I just have two small doubts:
* R9 Resistor: In my schematic, R9 is a 10K pull-down resistor at the MOSFET gate. Did you mean a different resistor to be divided, or should I leave this 10K as it is?
* D1 & D2 Diodes: I still have the back-to-back 1N4148 diodes at the gate. Should I completely delete them so they don't clamp the gate voltage?
@GeoMac:
You are absolutely right, and I completely missed that flaw! Using a standard BJT (Q1) to switch the delicate sampling signal was a rookie mistake on my part.
I would love to learn the right way to do this. Should I be using an Analog Switch IC like the CD4066 or a specific JFET instead? Your expert advice on how to properly wire this sampling stage would be incredibly helpful.
To make things easier, I am attaching both the updated PDF and the EasyEDA source file (.zip) to this post.
If you spot any more silly mistakes, please let me know. Also, if it is easier for you to explain the sampling logic by directly tweaking the source file, please feel free to do so! I am here to learn from the best.
Thanks again for being so patient and supportive!
Best regards,
Aashif
I cannot thank you both enough for taking the time to review my schematic. As a learner, getting guidance from experts like you is a huge privilege, and your practical insights are literally saving this project!
Detectorist#1:
I have carefully followed your instructions and updated the design:
1. Power Supply: Removed C1 to C8. Kept only C9 (4700uF/35V Low ESR) and added a 100nF/50V ceramic capacitor in parallel.
2. L1 Inductor: Replaced L1 with a 1 Ohm (0.5W) resistor.
3. MOSFET: Swapped the Drain and Source connections so they are now correctly routed.
4. Damping Resistor (R
: Replaced the single 330-ohm resistor with three 110-ohm (3W) resistors connected in series to handle the flyback voltage safely. I just have two small doubts:
* R9 Resistor: In my schematic, R9 is a 10K pull-down resistor at the MOSFET gate. Did you mean a different resistor to be divided, or should I leave this 10K as it is?
* D1 & D2 Diodes: I still have the back-to-back 1N4148 diodes at the gate. Should I completely delete them so they don't clamp the gate voltage?
@GeoMac:
You are absolutely right, and I completely missed that flaw! Using a standard BJT (Q1) to switch the delicate sampling signal was a rookie mistake on my part.
I would love to learn the right way to do this. Should I be using an Analog Switch IC like the CD4066 or a specific JFET instead? Your expert advice on how to properly wire this sampling stage would be incredibly helpful.
To make things easier, I am attaching both the updated PDF and the EasyEDA source file (.zip) to this post.
If you spot any more silly mistakes, please let me know. Also, if it is easier for you to explain the sampling logic by directly tweaking the source file, please feel free to do so! I am here to learn from the best.
Thanks again for being so patient and supportive!
Best regards,
Aashif

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