Dynamic Temporal Sampling Detector

[dbanner]

This thread explores the method of tracking the target decay curve (pulse induction) by variation in time(dt).

It is entirely experimental, to test the method and to see how far it can be developed.

It is inspired by the PICKINI.

In a time-domain pulse induction metal detector, the DAC's job is to generate the precise slicing level reference voltage. This reference voltage acts as a razor-thin tripwire line just above the noise floor. When the high-voltage coil flyback pulse decays and drops below this exact DAC voltage level, the internal comparator trips, allowing the timer to calculate the target pulse width (dt). Here is my understanding of how the code will work: to generate the slicing level:

Remember I am using a bi-polar TX drive

DAC Bit Depth: 8-Bit Dual Cores (Precision 256 Steps)(PIC18F16Q41)

DAC1 directly to the internal positive input of Comparator 1

DAC2 directly to the internal positive input of Comparator 2

The slicing voltage stays completely inside the chip. Resolution is 19.53mV per step(5V)

The 12-bit ADC fires a rapid, hardware-averaged 16-sample burst reading across the VOP and VON signal paths. This lets the firmware know exactly where the analog baseline is resting during the "quiet" period after the coil flyback and all target eddy currents have decayed completely to zero.

Next, the firmware reads the voltage coming from the 10kΩ linear sensitivity potentiometer via the ADC. If the user turns the knob all the way up, it means they want maximum depth, so the slicing level needs to sit as close to the baseline as possible.

Now, the code combines these two real-time values:
DAC1 slicing level (VOP) = VOP baseline + sensitivity offset
DAC2 slicing level (VON) = VON baseline + sensitivity offset


VOP slicing level:

Real-Time 12-Bit ADC Baseline Capture

Math Equation: Baseline + Sensitivity Offset

Write Number directly to Register: DAC1CON

Internal Silicon Core routes slicing level tripwire to Comparator 1

repeat for VON

Because this entire calculation and register update takes less than a single microsecond, the firmware does it seamlessly once per pulse cycle (up to 1,000 times a second). If a wave sweeps over the sand or the battery supply dips, the baseline shifts, the ADC catches it instantly, and the DAC dynamically recalculates the new slicing height for the very next pulse. There are absolutely no voltage jumps across external capacitors, meaning zero blind settlement delays and perfect real-time drift immunity!

At least in theory!



================================================== ==============
TRANSMIT CYCLE - NET VOLTAGE AT MCU - ACTIVE INTERNAL COMPARATOR
================================================== ==============
Cycle A (Positive) - VOP is POSITIVE (>0V) - COMPARATOR 1 processes VOP.

VON is Negative (<0V) - (Comparator 2 ignores the clipped VON line).

Cycle B (Negative) - VOP is Negative (<0V) - (Comparator 1 ignores the clipped VOP line).

VON is POSITIVE (>0V) - COMPARATOR 2 processes VON.

Also, to run a proper subtractive ground balance loop, the firmware must capture the decay time width (dt) at two distinct signal heights within the exact same pulse window: an Early Sample (t₁) and a Late Sample (t₂)
Because the PIC18F16Q41 features twin peripheral sets, the software configures them to act as two independent stopwatches running in parallel.

[Detectorist#1]

Hi dbanner,
Professional designers of pulse-induction metal detectors are most likely laughing at our discussion right now, but this is the logical direction of development of projects created by DIY designers.

[dbanner]

The analog part of the schematic is copied from BipolarPI_Sch_Rev2.1.pdf

The firmware source is standard C using the development suite: MPLAB X IDE paired with the XC8 Compiler.

PIC18F16Q41

The objective is to end up with a design for a half-decent, fairly good beach detector using this method. It must deal with the saltwater and wet beach sand ((PI time domain cancel saline + VRM simultaneously).

It must stay simple.

[Detectorist#1]

Hi dbanner,
Yes, As I writhed, the source is Pulse 5 design of ITMD3 - very optimal design from Carl. Now, we have to help for the design of the next level - the design with more, implemented features in the uP's part.

[dbanner]

The time-domain (dt) capture setup should completely sidestep the resolution and horsepower limitations of the microprocessor's direct sampling when resolving the decay curve in the amplitude domain.. At least this is the hope.

The PIC18F16Q41 treats the signal as a clean digital pulse width. The internal SMT1 peripheral handles the timing without needing a complex 32-bit processor or a bloated external ADC chip. It sets a fixed voltage height (internal 8-bit DAC slicing level) and uses the internal comparators and SMT1 timer to measure how long (the time duration, dt) the signal takes to fall past that line.

The ADC will be used for slow telemetry, user knobs (sensitivity and ground balance), and baseline tracking (auto-zeroing the baseline) . At the very end of the pulse listening window, the firmware commands the 12-bit ADC to sample the VOP and VON lines and instantly recalibrates the internal 8-bit DAC threshold references around it before the next transmit cycle triggers.

Ok, so far I can follow this.

So right now it's about fleshing out conceptually how the firmware is going to work. Trying to understand the flow.

The ground matrix at the beach (dry sand to wet sand and finally salt water) might be too ambitious for this method, I can see that typical ground balance would require 2 slicing levels, resulting in 2 time vectors, which is do-able. But the salt water might be a whole different ballgame.

Now I must look at the BCLK signal for the charge pump and the pulse drive for the H-bridge. The pulse width and PRF have to be considered carefully. Also I haven't considered what "sample delay" means in the context of this methodology, since strictly speaking we are dealing with slicing level triggers and not sampling gates.

[Tinkerer]

Have you given thought to the saturation of the pre-amp?

[BC547]

I still think that a 16bit PWM output can produce a more accurate slicing level than the internal 8 bit DAC.
Especially when you have a 12 bit ADC value as ground level.
The PWM output pin needs to be filtered with an R/C and fed back into the input pins of the comparators.

This PIC has a lot of interesting peripherals !
eg. The High/Low voltage detect for battery voltage monitoring.

[dbanner]

This PIC has a lot of interesting peripherals !
eg. The High/Low voltage detect for battery voltage monitoring.

HLVD module. Thanks for pointing that out. I will use it.

[dbanner]

Have you given thought to the saturation of the pre-amp?

I haven't looked too closely at that. What about it? I think I need a couple of series resistors at VOP and VON. The inverted negative saturation voltage can possibly damage the PIC input port (excessive current through the internal clamp diode). Maximum possible output swing at saturation is roughly +4.3V and-4.3V.

The firmware safety delay routines make sure the PIC18 ignores the initial saturation block. The register mapping of the internal 8-bit DACs will position the slicing tripwires precisely at the exit of that recovery curve.

You have something else in mind?

[dbanner]

I still think that a 16bit PWM output can produce a more accurate slicing level than the internal 8 bit DAC.
Especially when you have a 12 bit ADC value as ground level.
The PWM output pin needs to be filtered with an R/C and fed back into the input pins of the comparators.

Yes. Turn a 16-bit PWM digital square wave into a smooth analog slicing voltage depending on the duty cycle. But in practice will it be able to settle fast enough considering the filter network required?

The microcontroller features an internal Fixed Voltage Reference (FVR) module that acts as a stable, isolated internal voltage ceiling.
By changing the DAC’s positive reference register from VDD to the internal FVR 1.024V Buffer, the 8-bit resolution scale compresses dramatically.
The gain of the pre-amp is 100. One single step on the internal 8-bit DAC is at the sub millivolt level, do you think this will be insufficient?

In this proposed setup, firmware will make real-time baseline tracking—sampling the op-amp drift at the very end of everysingle pulse window and instantaneously updating the slicing level before the next pulse fires (occurring up to 1,000 times a second depending on the PRF).

The PIC18F16Q71 contains an internal 10-Bit Digital-to-Analog Converter.

[dbanner]

The dual DAC coarse/fine software trick:
Combine both internal 8-bit DACs into a Software-Driven Coarse/Fine Matrix using existing MAX412 differential stage.
Configure DAC1 to handle the positive VOP line as a coarse threshold (scaled to your 5V rail).
Configure DAC2 to handle the negative VON line as a fine threshold (scaled to the 1.024V FVR rail).
Because the firmware alternates positive and negative cycles across the full H-bridge transmitter, the code can evaluate both values dynamically, using the steps of DAC2 to interpolate and bridge the wider gaps of DAC1.

All these things are for way down the road, nothing is off the table as yet.
I need to lock down some variables first so I can know what VOP and VON signals are expected.

[BC547]

Combine both internal 8-bit DACs into a Software-Driven Coarse/Fine Matrix using existing MAX412 differential stage.

Or route the DAC outputs to the internal OPA module ?

Just trying to make the most of the internal resources ...

[dbanner]

PIC18F16Q71 dropped the SMT1, so it's a no go.

Here is basic framework of the firmware flowchart architecture. The chart is beautiful, it was generated by Mermaid. Never mind what is inside the boxes(could be all wrong). I am not capable to write such complex code, I'm sure I could learn but then that would take me a very, very long time. So long that I may be dead before I could manage to complete anything. So I hand off to AI.

It is clear that AI will make some of us less capable as time goes on, but I digress.

I am happy so long as I can have some basic idea of what is going on at the block level. I'll only go down rabbit hole if I have to.

[dbanner]

The external PWN and RC filter used in PICKINI V4 is very clever.

PICKINI V4 baseline alignment methodology:

The Startup Trap (calibration busy = 1): When the machine turns on, it sets a flag called calibration busy and steps through the function calibrate offset(). It forces the MCU to take an ADC sample, adjust its 5-bit internal DAC by one count, and then wait a massive chunk of time (CALIBRATION DELAY = 1500) before it can take the next step.

Frozen Running States: The moment the loop finishes matching its ADC TARGET, the calibration loop shuts off completely (calibration busy = 0). During active hunting, the physical 5-bit DAC value (DACCON1 = DAC value) is completely frozen and never updates again.

The Software Array Buffer: Instead of shifting the analog hardware baseline during hunting, the code shifts a moving baseline inside its RAM. It dumps every pulse length measurement into a 16-entry or 32-entry mathematical array (pulse average array). It calculates a slow, rolling mathematical average (pulse average) in software. Target detection is determined solely by checking if a single pulse spike sticks out above this slow software array.

And also this is the method for target:

Every time the code reads a fresh decay value (pulsevalue), it stores it inside a ring-buffer array (pulse average array).

The pulse average variable acts as a slow-moving digital baseline. It effectively remembers what the soil looked like over the last 16 to 32 pulses.

By executing the subtraction pulsediff = pulsevalue - pulse average, the code deletes the shared background signal. Only a fast-moving target that suddenly sticks out above the rolling average will generate a non-zero pulsediff, which immediately activates the speaker.

[BC547]

It forces the MCU to take an ADC sample, adjust its 5-bit internal DAC by one count, and then wait a massive chunk of time (CALIBRATION DELAY = 1500) before it can take the next step.

The massive delay between every DAC step was needed because the external pin output of the DAC goes into 3-state when switching from one value to another, causing the opamp output = ADC input to clip massively.
That is why I suggested to use the PWM output + filtering when doing a variable opamp offset voltage.
This is also why the final DAC value after calibration is stored in EEPROM - to be used as a starting value for the next calibration, which normally takes only 1 or 2 steps then.

Pinpoint in Pickini V4 = do not update the slow-moving average value anymore. Push the button outside a target - when going over the target, the value is not added to the averaging array anymore and sticks out on the spot.