New Bipolar Boost TX and Front End

[Mdtoday]

The ADuM4120 comes in 6 different variants/grades. The different grades/variants affect the Vdd2 Under Voltage LockOut (UVLO):
ADuM4120A - UVLO = 4.4V w/glitch filter;
ADuM4120B - UVLO = 7.3V w/glitch filter;
ADuM4120C - UVLO = 11.3V w/glitch filter;
ADuM4120-1A - UVLO = 4.4V w/o glitch filter;
ADuM4120-1B - UVLO = 7.3V w/o glitch filter;
ADuM4120-1C - UVLO = 11.3V w/o glitch filter;

The most critical place in our application is the damp switch MOSFETs. The capacitor supplying the vdd2 voltage needs to build up a charge to overcome the UVLO. And simulations indicate that the charge never exceeds 10V. The glitch filter does not seems to have no effect in our application. The B version should work in the application but, damping will be delayed until UVLO is overcome. The A grade will always work. Something that we must remember when we go to actual hardware with the updated TX design and order the right part.

I was actually just looking at the data sheets , suppliers etc on the ADuM4120 and noticed the different variants

[KingJL]

That is affected by the Dw parameter. I suggest setting the parameters as stated in post #576 (in both simulations). That should fix the problem... also do not consider the results before at least 8 ms as the boost build-up is not stable until then.

set the Dw parameter to 2.84u and it should switch positive (it actually switches positve at 2.85u).

The dual JFET version runs slower... this is due to the opa828 subcircuit. I have noticed that TI subcircuits really tax LtSpice... I think the TI models are more complex and computational intensive.

[KingJL]

... [ATTACH]48717[/ATTACH]

That is affected by the Dw parameter. I suggest setting the parameters as stated in post #576 (in both simulations). That should fix the problem... also do not consider the results before at least 8 ms as the boost build-up is not stable until then.

[KingJL]

ADuM4120 variants

The ADuM4120 comes in 6 different variants/grades. The different grades/variants affect the Vdd2 Under Voltage LockOut (UVLO):
ADuM4120A - UVLO = 4.4V w/glitch filter;
ADuM4120B - UVLO = 7.3V w/glitch filter;
ADuM4120C - UVLO = 11.3V w/glitch filter;
ADuM4120-1A - UVLO = 4.4V w/o glitch filter;
ADuM4120-1B - UVLO = 7.3V w/o glitch filter;
ADuM4120-1C - UVLO = 11.3V w/o glitch filter;

The most critical place in our application is the damp switch MOSFETs. The capacitor supplying the vdd2 voltage needs to build up a charge to overcome the UVLO. And simulations indicate that the charge never exceeds 10V. The glitch filter does not seems to have no effect in our application. The B version should work in the application but, damping will be delayed until UVLO is overcome. The A grade will always work. Something that we must remember when we go to actual hardware with the updated TX design and order the right part.

[Mdtoday]

Thanks JL, much appreciated. I will try them out now.

@JL all work fine now, thank you.

[Mdtoday]

Thank you @Mdtoday for checking them out... Hopefully, all needed files for the sim are now there. My problem is that since I use some of these elsewhere, I have them in the global library,,, that LtSpice seems to update frequently!

Newest zip of sim files

Thanks JL, much appreciated. I will try them out now.

[KingJL]

@JL, The TX(ADuM)_RX(THAT)) version appears to be missing the .asy and .sub for the THAT1512.

Thank you @Mdtoday for checking them out... Hopefully, all needed files for the sim are now there. My problem is that since I use some of these elsewhere, I have them in the global library,,, that LtSpice seems to update frequently!

Newest zip of sim files

[Mdtoday]

@JL, The TX(ADuM)_RX(THAT)) version appears to be missing the .asy and .sub for the THAT1512.

[KingJL]

... but the sim shouts Time step too small schmitt instance TX(ADuM)_RX(THAT))

@eclipse, did the updated zip and recheck of settings resolve your "Time step too small" issue. I am now running with the ".option Gmin=1e-010" commented out ( using the Contro Panel>SPICE defaults with "Normal" solver).

[Mdtoday]

No need to rush... I will make the changes in the FPGA and it will be ready and waiting. This does not need to impact our current project testing, but can go on in parallel as time permits.

Not a problem JL, thanks, last minute urgent customer jobs, always land 2 days before holiday period.

[KingJL]

Sorry, missed this post, I don't mind doing it but probably wont get to it tonight until late..

No need to rush... I will make the changes in the FPGA and it will be ready and waiting. This does not need to impact our current project testing, but can go on in parallel as time permits.

[Mdtoday]

Great... the 15V for the re-configured TX draws < 15mA. The 20V also draws < 15mA. So I think we can use the 20/15 volt circuits as they are with maybe a little bit of tantalum storage for the 15V line. The total draw on the 20V should be around 50mA when you take in consideration the 15V regulator.Do you want to follow through and test that feasibility or do you want me to do it?

Sorry, missed this post, I don't mind doing it but probably wont get to it tonight until late..

[Mdtoday]

I believe that we could get away with disabling the boost reg at TX_OFF... and only blank for 20% of PRT from TX _OFF. I will work on implementing that in the FPGA. I will supply a blanking pulse to PMod J4 (probably pin 3).

Ok, that sounds good.

[Mdtoday]

I agree!I am not sure we need to quite do that any longer... as we are using the Nextion gpio pin interface for PP now. I think you have interfaced a PP push button switch to the Nextion gpio in other projects... we can do it the same way!

Yes, of course, we just use the expansion port inputs as I have done previously...

I have also identified a few linear 5v regs we can use, they have an error flag output on pin 5 in place of sense input so we can leave it floating or snip off the lead for testing on current pcb. Microchip/TI have similar.

http://ww1.microchip.com/downloads/en/DeviceDoc/MIC2915x-30x-50x-75x-High-Current-Low-Dropout-Regulators-DS20005685B.pdf

Next rev board we can use sot-223 lower current devices

[KingJL]

I could send out a 3.3V blanking pulse during the time that we want the boost reg disabled... starting at TX (to let the 20V stabilize prior to RX) and extending into the RX for for 20% of the PRT (boost reg disabled for the 1st 30% of PRT). You could the use AND logic to control the regulator... enabled except for when a "blank" signal from PMOD J4. That way it is running by default.

I believe that we could get away with disabling the boost reg at TX_OFF... and only blank for 20% of PRT from TX _OFF. I will work on implementing that in the FPGA. I will supply a blanking pulse to PMod J4 (probably pin 3).