New Bipolar Boost TX and Front End

[Mdtoday]

@Mdtoday, do you have probe points for M6_G and M7_G?

yes, I do

[Mdtoday]

[QUOTE=Mdtoday;263669]Yes, I think I might now go and rewind the primary of one transformer with .63mm diam wire see if we can squeeze a little more out of it./QUOTE]

I have removed all 1 ohm resistors on transformer driver outputs and replaced with 0R links, rewound primaries using .63mm diam (22g) wire. and made up some carrier modules with sockets to prevent board damage while we are in the testing phase.





There is close to 800mV pulse height improvement.


As you have pointed out, I think we are at our limits on the current toroids.

We still have 14v gate drive on M6_G and M7_G.

[KingJL]

... and made up some carrier modules with sockets to prevent board damage while we are in the testing phase...

[ATTACH]48494[/ATTACH]

[ATTACH]48495[/ATTACH]

I really like those sockets for testing!!!

There is close to 800mV pulse height improvement.
[ATTACH]48493[/ATTACH]...

I think that got us over a minimum threshold for testing.

We still have 14v gate drive on M6_G and M7_G.

????

[Mdtoday]

I really like those sockets for testing!!!I think that got us over a minimum threshold for testing.????

The waveform on M6 M7 stayed the same so I didn?t post new shot. I will perhaps wind another transformer with more secondary windings on one if these cores . It looks like I could squeeze 17 on there...tight but worth a try

[KingJL]

The waveform on M6 M7 stayed the same so I didn?t post new shot. I will perhaps wind another transformer with more secondary windings on one if these cores . It looks like I could squeeze 17 on there...tight but worth a try

I see no shot of M6 & M7... other shots were M2 & M4... right? M6 & M7 are the damp MOSFETs.

[KingJL]

Test Point

In the next version of the TX board, I think I will include an isolated test point to be able to check the MOSFET gate drive and route the pad for the test point to the top side.




It does not show the actual voltage of the drive pulse, but the ratio can be determined. It is at a 0V reference and testing with it will not change the electrical charactaristics of the circuit under test (like dissapating any capacitively stored voltage).

[KingJL]

... I will perhaps wind another transformer with more secondary windings on one if these cores . It looks like I could squeeze 17 on there...tight but worth a try

If I remember correctly, the secondary had a relatively thick (relative to the conductor diameter) insulation... I don't even know if I checked the secondary wire diameter ( they were very thin). In the new transformers that I will wind, I am going to use AWG 28.

[KingJL]

If I remember correctly, the secondary had a relatively thick (relative to the conductor diameter) insulation... I don't even know if I checked the secondary wire diameter ( they were very thin). In the new transformers that I will wind, I am going to use AWG 28.

Just re-checked them... of the two original windings, one has has just an enamel outer insulation, the other has an additional insulation layer. The winding with the enamel outer layer is slightly over 0.014" (0.355mm) with the conductor slightly less than 0.014". The winding with the additional layer of insulation was 0.024" overall with a conductor diameter of slightly less than 0.014". AWG 27 = 0.0142. It appears that using the enamle insulated wire, we could get more turns on the secondary. I had done what you appear to have done... retained the winding with the additonal layer of insulation.

[Altra]

Just re-checked them... of the two original windings, one has has just an enamel outer insulation, the other has an additional insulation layer. The winding with the enamel outer layer is slightly over 0.014" (0.355mm) with the conductor slightly less than 0.014". The winding with the additional layer of insulation was 0.024" overall with a conductor diameter of slightly less than 0.014". AWG 27 = 0.0142. It appears that using the enamle insulated wire, we could get more turns on the secondary. I had done what you appear to have done... retained the winding with the additonal layer of insulation.

I had the same problems with the Chinese toroids. I ended up revisiting the Vallon design and they are using over 20 turns on the secondary. So my current design is using 6 turns #24 on the primary and 23 turns of #30 for the secondary. My primary has a 1 ohm in series. The secondary wire gauge didn't seem to matter. I am getting over 20 volts of gate drive which is more than enough. Good idea sourcing a spec'ed toriod. Too much going on in these circuits to wonder if your Chinese parts are the problem. Can't wait until you start the signal processing stage.

Attached photo - no coil, gate voltage 21 volts for 100uS.

[KingJL]

M6 & M7 are the damp MOSFETs.

Which are driven by the other 2 pulse transformer circuits.

[KingJL]

Toroid Dpecifications

I have determined the specifications for the toroid cores we have:
measured OD = 11.9 mm
measured ID = 7.417 mm
measured H = 3.048 mm
measured inductance @13 turns = 1185

using the calculator @ https://coil32.net/online-calculator...meability.html
ui = 24782
AL=7011.83

using the calculator @ https://coil32.net/online-calculator...alculator.html
4t = 112 uH ( 14.228 cm AWG 22 (w/5cm x 2 leads)
15t = 1578 uH ( 25.87 cm AWG28 (w/ 5cm x 2 leads)
16t = 2351 uH ( 29.4 cm AWG28 (w/5cm x 2 leads)

15t : 4t is a 3.75:1 ratio which should be more than enough since the 5V supply will always be 5V or greater (high enough to generate 1 amp TX current. If TX current is too high at 5V, need to adjust R6, R7, R8, R10 values to maintain >=5V).
16t : 4t is a 16:1 ratio if we need it.

[Mdtoday]

I see no shot of M6 & M7... other shots were M2 & M4... right? M6 & M7 are the damp MOSFETs.

Sorry, yes, you are correct, I will measure again and post those.

[Mdtoday]

In the next version of the TX board, I think I will include an isolated test point to be able to check the MOSFET gate drive and route the pad for the test point to the top side.
[ATTACH=CONFIG]48496[/ATTACH]



It does not show the actual voltage of the drive pulse, but the ratio can be determined. It is at a 0V reference and testing with it will not change the electrical charactaristics of the circuit under test (like dissapating any capacitively stored voltage).
[ATTACH=CONFIG]48497[/ATTACH]

I really like this idea, it will be very handy.

[Mdtoday]

Which are driven by the other 2 pulse transformer circuits.

Yes, I did take those measurements and stored on USB drive along with the others, so I will post later today.

[KingJL]

I see no shot of M6 & M7... other shots were M2 & M4... right? M6 & M7 are the damp MOSFETs.

If there were screen shots of M6_G and M7_G then we have a problem... extremely easily corrected but still a problem. The M6 & M7 gates shold be 0 during the TX time and go high shortly after TX turns off and stay high until slightly before TX (A or B) turns on again. In other words it will be high for ~398 usec and low for ~60 usec.

As I recheck the schematic, I see that I took DAMP_S to pin 4 of U14 and U15... I think this is wrong... my rationale was wrong. If this is a fact, then I can correct it by changing the constraint file for the Cmod-A7. All I will have to do then is regenerate the project and post it.